Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating

• US 9,025,358 B2
• Filed: 10/15/2012
• Issued: 05/05/2015
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/652,457
• Publication Number:
  US 20130094280A1
• Time in Patent Office: 932 Days
• Field of Search: 365/148, 365/100
• US Class Current: 365/148
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0027 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 14/0036 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

Claims

1. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a non-volatile memory comprising a bipolar resistive change element;

wherein said floating body has a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said memory cell further comprising first and second regions at first and second locations of said cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type.

2. The semiconductor memory cell of claim 1, wherein said bipolar resistive change element is configured to store said data stored in said floating body upon transfer thereto.

3. The semiconductor memory cell of claim 1, wherein said bipolar resistive change element comprises a material selected from at least one of:

transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

4. The semiconductor memory cell of claim 1, wherein said bipolar resistive change element is electrically connected to said capacitorless transistor and a distance between said bipolar resistive change element and said capacitorless transistor, when electrically connected, is in the range from about 90 nm to 1 μ

m.

5. The semiconductor memory cell of claim 1,

wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

6. The semiconductor memory cell of claim 5, wherein said bipolar resistive change element is electrically connected to said one of said first and second regions via a conductive element.

7. The semiconductor memory cell of claim 5, further comprising an addressable line electrically connected to said bipolar resistive change element.

8. The semiconductor memory cell of claim 7, wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.

9. The semiconductor memory cell of claim 1, further comprising:

a substrate being made of a material having said second conductivity type; and

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

wherein said floating body is formed between said first and second regions and said buried layer; and

wherein said non-volatile memory is electrically connected to one of said first and second regions.

10. The semiconductor memory cell of claim 1, further comprising:

a substrate being made of a material having said second conductivity type;

a well in said substrate, said well having said first conductivity type;

and a buried layer located between said well and said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

wherein said floating body is formed between said first and second regions and said buried layer;

and wherein said non-volatile memory is electrically connected to one of said first and second regions.

11. The semiconductor memory cell of claim 10, wherein said substrate is a well formed in a second substrate.

12. The semiconductor memory cell of claim 1, wherein said cell has a three-dimensional structure comprising a fin structure extending substantially perpendicular to, and above a top surface of a substrate.

13. A semiconductor memory array comprising a plurality of semiconductor memory cells as recited in claim 1, arranged in a matrix of at least one row and at least one column.

14. An integrated circuit device comprising the semiconductor memory array of claim 13 and circuitry configured to determine whether said semiconductor array, or a portion of said semiconductor memory array, has been idle for a time period equal to or greater than a predetermined time period.

15. The semiconductor memory cell of claim 1, wherein said floating body comprises a bipolar memory device.

16. A semiconductor memory cell comprising:

a silicon controlled rectifier device configured to store data and operate as volatile memory when power is applied to said cell; and

a non-volatile memory comprising a bipolar resistance change element;

wherein said silicon controlled rectifier device comprises a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said memory cell further comprising first and second regions at first and second locations of said cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type.

17. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory, said method comprising:

storing data in a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory, wherein said floating body operates as a capacitorless DRAM cell or a bi-stable SRAM cell; and

storing data in a bipolar resistance change element by configuring the bipolar resistance change element in one of a low resistivity state or a high resistivity state, wherein each of said resistivity states corresponds to a different data value, respectively.

18. The method of claim 17, further comprising:

restoring said data from said bipolar non-volatile memory to said floating body as volatile memory.

19. The method of claim 18, wherein said restoring comprises evacuating holes from the volatile memory when the bipolar non-volatile memory is in a low resistance state, but maintaining a presently existing charge in the volatile memory when the bipolar non-volatile memory is in a high resistance state.

20. The method of claim 18, wherein said restoring and said maintaining are performed non-algorithmically.