Method for improving data retention of ReRAM chips operating at low operating temperatures

• US 9,025,360 B2
• Filed: 12/20/2013
• Issued: 05/05/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Intermolecular Incorporated
• Original Assignee: Intermolecular Incorporated
• Inventors: Pramanik, Dipankar, Chiang, Tony P.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/137,893
• Publication Number:
  US 20140269004A1
• Time in Patent Office: 501 Days
• Field of Search: 365/148, 365/226
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/00 : Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00
• CPC Class Codes: H10N 70/011 : Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/021 : Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/023 : by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/041 : Modification of the switching material, e.g. post-treatment, doping
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/801 : Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8416 : adapted for supplying ionic species
• CPC Class Codes: H10N 70/881 : Switching materials
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 : Oxides or nitrides

Abstract

Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations.

Claims

1. A method comprising

providing a memory device, wherein the memory device operates at an operating temperature;

heating the memory device to a programming temperature, wherein the programming temperature is greater than the operating temperature; and

programming a switching element of the memory device during the heating,

wherein programming a switching element of the memory device comprises applying a first voltage or current to a heater to heat the memory device to the programming temperature, followed by applying a second voltage or current to the switching element.

2. A method as in claim 1 wherein the operating temperature is less than 85 C, wherein the programming temperature is between 85 and 200 C.

3. A method as in claim 1 wherein programming a switching element of the memory device comprises applying a voltage or current to the switching element.

4. A method comprising

forming a memory structure, wherein the memory structure comprises an insulator layer disposed between two electrode layers, wherein the insulator layer is operable as a switching layer;

heating the memory structure, wherein heating the memory structure comprises applying a second voltage or current to a heater, wherein the heater is disposed in a vicinity of the memory structure;

while heating the memory structure, applying a voltage or current to the two electrode layers to set or reset the memory structure; and

after applying the voltage or current, stopping the heating of the memory structure.

5. A method as in claim 4 wherein the memory structure is heated to a temperature higher than an operating temperature of the memory structure.

6. A method as in claim 4 wherein the operating temperature is less than 85 C, wherein the memory structure is heated to a temperature between 85 and 200 C.

7. A method as in claim 4 further comprising

monitoring a temperature of the memory structure during the heating.

8. A method as in claim 4 wherein the memory structure comprises an array of memory devices, wherein a memory device comprises a switching element disposed between two electrode layers.

9. A method as in claim 8 wherein heating the memory structure comprises heating the array of memory devices.

10. A memory device comprising

a memory array, wherein the memory array comprises a plurality of memory structures, wherein each memory structure comprises an insulator layer disposed between two electrode layers, wherein the insulator layer is operable as a switching layer;

a heater element disposed in a vicinity of the memory array, wherein the heater element is configured to heat the plurality of memory structures; and

a temperature sensor disposed in a vicinity of the memory array.

11. A memory device as in claim 10 wherein the heater is configured to heat the memory array to a temperature up to 200 C.

12. A memory device as in claim 10 wherein the heater element comprises a heating pad, wherein the heating pad is operable by applying a voltage or current.

13. A memory device as in claim 10 wherein the temperature sensor comprises a diode or a resistor element.

14. A memory device as in claim 10 wherein the heater element is configured to heat all memory structures in the memory array.

15. A memory device as in claim 10 wherein the heater element is configured to heat individual memory structures in the memory array.

16. A memory device as in claim 10 wherein the heater element comprises an array of heating components, wherein each heating component is configured to heat an individual memory structure in the memory array.

17. A memory device as in claim 10 further comprising a circuit to select heating components.

18. A memory device as in claim 10 wherein the heater element and the memory array form a stack in which the heater element is separated from the memory array by an electrical insulator layer.