Memory disturb reduction for nonvolatile memory

• US 9,025,375 B2
• Filed: 10/22/2013
• Issued: 05/05/2015
• Est. Priority Date: 04/15/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chang, Yu-Ming, Wang, Cheng-Yuan, Chang, Yuan-Hao, Li, Yung-Chun, Lu, Hsing-Chen, Li, Hsiang-Pang, Kuo, Tei-Wei
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US14/060,296
• Publication Number:
  US 20140307505A1
• Time in Patent Office: 560 Days
• Field of Search: 365/185.02, 365/230.03, 365/185.17, 365/185.29, 365/185.11
• US Class Current: 365/185.02
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Claims

1. A method of operating a NAND array including a plurality of pages, wherein the plurality of pages of the NAND array are divided into a plurality of page groups, comprising:

allowing access to memory cells within a first page group of a plurality of page groups in an erase block of the NAND array, while minimizing access to memory cells within a second page group of the plurality of page groups in the erase block of the NAND array,

wherein pages in the page group are physically nonadjacent with each other in the NAND array.

2. The method of claim 1,

wherein said allowing access includes, allowing program operations on memory cells within the first page group of the plurality of page groups in the erase block of the NAND array, and

wherein said minimizing access includes, minimizing program operations on memory cells within the second page group of the plurality of page groups in the erase block of the NAND array.

3. The method of claim 1,

wherein said allowing access includes, allowing read operations on memory cells within the first page group of the plurality of page groups in the erase block of the NAND array, and

wherein said minimizing access includes, minimizing read operations on memory cells within the second page group of the plurality of page groups in the erase block of the dimensional NAND array.

4. The method of claim 1,

wherein an erase instruction for a page group, results in the page group having an invalid status indicating (i) delayed erase of the page group and (ii) unavailability of the pages of the page group for read and write memory operations until at least the delayed erase of the page.

5. The method of claim 4,

wherein, when both the first and second page groups have received the erase instruction, the erase block which contains these two page groups are erased, and the invalid status for all of the plurality of page groups is removed.

6. The method of claim 1,

wherein the first page group and the second page group have checkerboard patterns offset with respect to each other.

7. The method of claim 1,

wherein pages in the plurality of pages include series of physically adjacent memory cells in the NAND array.

8. The method of claim 7,

wherein series of physically adjacent memory cells are arranged such that, a page in the plurality of pages includes memory cells in a same memory cell layer of the NAND array, accessed by a same word line, and accessed by different bit lines,

wherein any two pages of the first one of the plurality of page groups are mutually physically nonadjacent, due to at least one of:

(i) at least one intervening word line in between the two pages,

(ii) at least one intervening memory cell layer in between the two pages, and

(iii) the two pages positioned in different memory cell layers and accessed by different word lines.

9. The method of claim 7,

wherein series of physically adjacent memory cells are arranged such that, a page in the plurality of pages includes memory cells in different layers of the NAND array, accessed by a same word line,

wherein any two pages of the first one of the plurality of page groups are mutually physically nonadjacent, due to at least one of:

(i) at least one intervening word line in between the two pages,

(ii) at least one intervening memory string stack in between the two pages, and

(iii) the two pages sharing no memory strings and accessed by different word lines.

10. The method of claim 7,

wherein series of physically adjacent memory cells are arranged such that, a page in the plurality of pages includes memory cells in a same layer of the NAND array, accessed by different word lines,

wherein any two pages of the first one of the plurality of page groups are mutually physically nonadjacent, due to at least one of:

(i) at least one intervening memory cell layer in between the two pages,

(ii) at least one intervening memory string stack in between the two pages, and

(iii) the two pages positioned in different memory cell layers and positioned in different memory string stacks.

11. A computer-readable non-transitory storage medium embodying instructions for a NAND array including a plurality of pages, wherein the NAND array is divided into a plurality of page groups, the instructions when executed perform:

allowing access to memory cells within a first page group of a plurality of page groups in an erase block of the NAND array, while minimizing access to memory cells within a second page group of the plurality of page groups in the erase block of the NAND array, wherein pages in the page group are physically nonadjacent with each other in the NAND array.

12. The computer-readable non-transitory storage medium of claim 11,

wherein said allowing access includes, allowing program operations on memory cells within the first page group of the plurality of page groups in the erase block of the three dimensional NAND array, and

wherein said minimizing access includes, disallowing program operations on memory cells within the second page group of the plurality of page groups in the erase block of the three dimensional NAND array.

13. The computer-readable non-transitory storage medium of claim 11,

wherein said allowing access includes, allowing read operations on memory cells within the first page group of the plurality of page groups in the erase block of the three dimensional NAND array, and

wherein said minimizing access includes, disallowing read operations on memory cells within the second page group of the plurality of page groups in the erase block of the three dimensional NAND array.

14. The computer-readable non-transitory storage medium of claim 11,

wherein an erase instruction for a page group, results in the page group having an invalid status indicating (i) delayed erase of the page group and (ii) unavailability of the pages of page group for read and write memory operations until at least the delayed erase of the page.

15. The computer-readable non-transitory storage medium of claim 14,

wherein, when both the first and second page groups have received the erase instruction, the erase block which contains these two page groups are physically erased, and the invalid status for all of the plurality of page groups is removed.

16. The computer-readable non-transitory storage medium of claim 11,

wherein the first page group and the second page group have checkerboard patterns offset with respect to each other.

17. The computer-readable non-transitory storage medium of claim 11,

wherein pages in the plurality of pages include series of physically adjacent memory cells in the NAND array.

18. The computer-readable non-transitory storage medium of claim 17,

wherein series of physically adjacent memory cells are arranged such that, a page in the plurality of pages includes memory cells in a same memory cell layer of the NAND array, accessed by a same word line, and accessed by different bit lines,

wherein any two pages of the first one of the plurality of page groups are mutually physically nonadjacent, due to at least one of:

(i) at least one intervening word line in between the two pages,

(ii) at least one intervening memory cell layer in between the two pages, and

(iii) the two pages positioned in different memory cell layers and accessed by different word lines.

19. The computer-readable non-transitory storage medium of claim 17,

wherein series of physically adjacent memory cells are arranged such that, a page in the plurality of pages includes memory cells in different layers of the NAND array, accessed by a same word line,

wherein any two pages of the first one of the plurality of page groups are mutually physically nonadjacent, due to at least one of:

(i) at least one intervening word line in between the two pages,

(ii) at least one intervening memory string stack in between the two pages, and

(iii) the two pages sharing no memory strings and accessed by different word lines.

20. The computer-readable non-transitory storage medium of claim 17,

wherein series of physically adjacent memory cells are arranged such that, a page in the plurality of pages includes memory cells in a same layer of the NAND array, accessed by different word lines,

wherein any two pages of the first one of the plurality of page groups are mutually physically nonadjacent, due to at least one of:

(i) at least one intervening memory cell layer in between the two pages,

(ii) at least one intervening memory string stack in between the two pages, and

(iii) the two pages positioned in different memory cell layers and positioned in different memory string stacks.

21. A computing device, comprising:

a processor;

a NAND array including a plurality of pages, wherein the plurality of pages of the NAND array are divided into a plurality of page groups; and

control circuitry coupled to at least one of the processor and the NAND array, the control circuitry allowing access to memory cells within a first page group of a plurality of page groups in an erase block of the NAND array, while minimizing access to memory cells within a second page group of the plurality of page groups in the erase block of the NAND array,

wherein virtual erase blocks in a plurality of virtual erase blocks are mapped to one of the plurality of page groups, page groups in the plurality of page groups including pages from the plurality of pages that are mutually physically nonadjacent with each other in the NAND array, and

wherein pages in the page group are physically nonadjacent with each other in the NAND array.