Semiconductor memory device
First Claim
1. A semiconductor memory device, comprising:
- a memory block including a plurality of memory strings, each string including a plurality of memory cell transistors connected in series with a first selection transistor on a first end and a second selection transistor on a second end, the plurality of memory strings including a first memory string and a second memory string;
a first bit line connected to the first selection transistor of the first memory string and the first selection transistor of the second memory string;
a sense amplifier connected to the first bit line;
a plurality of word lines, each word line connected to a memory cell transistor in each memory string; and
a controller configured to control an erase operation of the memory block, wherein the erase operation includes;
applying a first erase voltage to the plurality of word lines;
addressing the first memory string by applying a selection voltage to a gate electrode of the first and second selection transistor of the first memory string;
applying an erase verify voltage to the plurality of word lines and reading data of memory cell transistors in the first memory string by using the sense amplifier to determine whether the first memory string passes an erase verify; and
when the first memory string passes the erase verify, addressing the second memory string without first discharging the plurality of word lines, andwhen the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a predetermined number.
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Accused Products
Abstract
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.
51 Citations
18 Claims
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1. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, each string including a plurality of memory cell transistors connected in series with a first selection transistor on a first end and a second selection transistor on a second end, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to the first selection transistor of the first memory string and the first selection transistor of the second memory string; a sense amplifier connected to the first bit line; a plurality of word lines, each word line connected to a memory cell transistor in each memory string; and a controller configured to control an erase operation of the memory block, wherein the erase operation includes; applying a first erase voltage to the plurality of word lines; addressing the first memory string by applying a selection voltage to a gate electrode of the first and second selection transistor of the first memory string; applying an erase verify voltage to the plurality of word lines and reading data of memory cell transistors in the first memory string by using the sense amplifier to determine whether the first memory string passes an erase verify; and when the first memory string passes the erase verify, addressing the second memory string without first discharging the plurality of word lines, and when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a predetermined number. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A memory system, comprising:
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a memory block including a plurality of memory strings, each string including a plurality of memory cell transistors connected in series with a first selection transistor on a first end and a second selection transistor on a second end, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to the first selection transistor of the first memory string and the first selection transistor of the second memory string; a sense amplifier connected to the first bit line; a plurality of word lines, each word line connected to a memory cell transistor in each memory string; a controller configured to control an erase operation of the memory block, wherein the erase operation includes; applying a first erase voltage to the plurality of word lines; addressing the first memory string by applying a selection voltage to a gate electrode of the first and second selection transistor of the first memory string; applying an erase verify voltage to the plurality of word lines and reading data of memory cell transistors in the first memory string by using the sense amplifier to determine whether the first memory string passes an erase verify; when the first memory string passes the erase verify, addressing the second memory string without first discharging the plurality of word lines; and when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a predetermined number, wherein the controller is further configured to carry out an accumulated string erase verify for all memory strings, and the controller is configured to determine whether the accumulated string erase verify passed or failed based on a result of the accumulated string erase verify. - View Dependent Claims (17)
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18. A method of controlling a memory device including a memory block with a plurality of memory strings, each string including a plurality of memory cell transistors connected in series with a first selection transistor on a first end and a second selection transistor on a second end, the plurality of memory strings including a first memory string and a second memory string, a first bit line connected to the first selection transistor of the first memory string and the first selection transistor of the second memory string, a sense amplifier connected to the first bit line, a plurality of word lines, each word line connected to a memory cell transistor in each memory string, and a controller, the method comprising an erase operation performed on the memory block, the erase operation including the steps of:
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applying a first erase voltage to the plurality of word lines; addressing the first memory string by applying a selection voltage to a gate electrode of the first and second selection transistor of the first memory string; applying an erase verify voltage to the plurality of word lines and reading data of memory cell transistors in the first memory string by using the sense amplifier to determine whether the first memory string passes an erase verify; when the first memory string passes the erase verify, addressing the second memory string in the memory block without first discharging the plurality of word lines; and when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a predetermined number.
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Specification