Method of optimizing solid state drive soft retry voltages

• US 9,025,393 B2
• Filed: 04/03/2013
• Issued: 05/05/2015
• Est. Priority Date: 03/25/2013
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Wu, Yunxiang, Chen, Zhengang, Wu, YingQuan, Chen, Ning
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LEBOEUF, JEROME LARRY
• Application Number:
  US13/856,179
• Publication Number:
  US 20140286102A1
• Time in Patent Office: 762 Days
• Field of Search: 365/185.22, 365/185.2, 365/185.12, 365/185.14, 365/185.15, 365/185.21, 365/185.03, 365/185.09, 365/185.18, 365/185.24, 365/185.33, 365/185.19, 714/784, 714/758, 714/773, 714/780, 714/760
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.

Claims

1. A method for optimizing solid state drive soft retry voltages, comprising:

determining a first reference voltage for a first soft retry voltage read, the first reference voltage based on a hard decision read;

reading a first soft retry voltage at the first reference voltage;

determining if the first soft retry voltage read fails, the determining based on an analysis of the first soft retry voltage read;

determining a spacing between the first reference voltage and reference voltages for each one of a plurality of additional soft retry voltage reads, the spacing based on the first soft retry voltage read and a desired bit error rate, the spacing being constant;

determining a number of soft retry voltages to be read, the number based on a type of solid state drive;

reading a second soft retry voltage from the plurality of additional soft retry voltage reads at a second reference voltage, the second reference voltage at least one iteration of the spacing distant from the first reference voltage;

if the first soft retry voltage read fails, then reading the second soft retry voltage at a multiple of iterations of the spacing distant from the first reference voltage, the multiple based on an analysis of a characterization data, the multiple greater than or equal to two;

reading each one of the plurality of additional soft retry voltage reads at their respective reference voltages, each of the reference voltages at least one iteration of the spacing distant from a previous reference voltage; and

correcting a channel of a memory based on a reading.

2. The method for optimizing solid state drive soft retry voltages of claim 1, wherein the first soft retry voltage read further comprises a number of soft retry voltages read, the number of soft retry voltages read based on a memory page type and a memory type.

3. The method for optimizing solid state drive soft retry voltages of claim 1, wherein the first reference voltage of a first soft retry voltage read further comprises a first particular reference voltage based on at least one program erase cycle.

4. The method for optimizing solid state drive soft retry voltages of claim 1, wherein the first reference voltage of a first soft retry voltage read further comprises a second particular reference voltage based on an input from a channel tracking algorithm.

5. The method for optimizing solid state drive soft retry voltages of claim 1, wherein determining a spacing between the first reference voltage and reference voltages for each one of a plurality of additional soft retry voltage reads further comprises determining the spacing based on analysis of the program erase cycle.

6. The method for optimizing solid state drive soft retry voltages of claim 1, wherein reading a second soft retry voltage from the plurality of additional soft retry voltage reads at a second reference voltage further comprises shifting a number of soft retry voltage reads, in parallel, a number of iterations of the spacing greater or less than the reference voltage of the first soft retry voltage read.

7. The method for optimizing solid state drive soft retry voltages of claim 1, wherein the second reference voltage is at least two iterations of the spacing distant from the first reference voltage and the number of soft retry voltages to be read is less than ten.

8. The method for optimizing solid state drive soft retry voltages of claim 1, wherein reading each one of the plurality of additional soft retry voltage reads at the reference voltages further comprises reference voltages based on at least two of:

the number of reads, a reference voltage of a last read and the spacing.

9. The method for optimizing solid state drive soft retry voltages of claim 8, wherein the reference voltage of the last read is based on a desired bit error rate.

10. The method for optimizing solid state drive soft retry voltages of claim 1, wherein correcting a channel of a memory based on the reading further comprises correcting a SLC channel, a MLC channel, a TLC channel, and a channel sized to carry at least four bits per cell.

11. A non-transitory computer readable medium having computer readable program code embodied therein for optimizing solid state drive soft retry voltages, the computer readable program code comprising instructions which, when executed by a computer device or processor, perform and direct the steps of:

determining a first reference voltage for a first soft retry voltage read, the first reference voltage based on a hard decision read;

reading a first soft retry voltage at the first reference voltage;

determining if the first soft retry voltage read fails, the determining based on an analysis of the first soft retry voltage read;

determining a spacing between the first reference voltage and reference voltages for each one of a plurality of additional soft retry voltage reads, the spacing based on the first soft retry voltage read and a desired bit error rate, the spacing being constant;

determining a number of soft retry voltages to be read, the number based on a type of solid state drive;

reading a second soft retry voltage from the plurality of additional soft retry voltage reads at a second reference voltage, the second reference voltage at least one iteration of the spacing distant from the first reference voltage;

if the first soft retry voltage read fails, then reading the second soft retry voltage at a multiple of iterations of the spacing distant from the first reference voltage, the multiple based on an analysis of a characterization data, the multiple greater than or equal to two;

reading each one of the plurality of additional soft retry voltage reads at their respective reference voltages, each of the reference voltages at least one iteration of the spacing distant from a previous reference voltage; and

correcting a channel of a memory based on a reading.

12. The computer readable medium of claim 11, wherein the first soft retry voltage read further comprises a number of soft retry voltages read, the number of soft retry voltages read based on a memory page type and a memory type.

13. The computer readable medium of claim 11, wherein the first reference voltage of a first soft retry voltage read further comprises a first particular reference voltage based on at least one program erase cycle.

14. The computer readable medium of claim 11, wherein the first reference voltage of a first soft retry voltage read further comprises a second particular reference voltage based on an input from a channel tracking algorithm.

15. The computer readable medium of claim 11, wherein determining a spacing between the first reference voltage and reference voltages for each one of a plurality of additional soft retry voltage reads further comprises determining the spacing based on analysis of the program erase cycle.

16. The computer readable medium of claim 11, wherein reading a second soft retry voltage from the plurality of additional soft retry voltage reads at a second reference voltage further comprises shifting a number of soft retry voltage reads, in parallel, a number of iterations of the spacing greater or less than the reference voltage of the first soft retry voltage read.

17. The computer readable medium of claim 11, wherein the second reference voltage is at least two iterations of the spacing distant from the first reference voltage and the number of soft retry voltages to be read is less than ten.

18. The computer readable medium of claim 11, wherein reading each one of the plurality of additional soft retry voltage reads at the reference voltages further comprises reference voltages based on at least two of:

the number of reads, a reference voltage of a last read and the spacing.

19. The computer readable medium of claim 18, wherein the reference voltage of the last read is based on a desired bit error rate.

20. The computer readable medium of claim 11, wherein correcting a channel of a memory based on the reading further comprises correcting a SLC channel, a MLC channel, a TLC channel, and a channel sized to carry at least four bits per cell.