Method, apparatus and instructions for parallel data conversions

• US 9,026,570 B2
• Filed: 11/21/2012
• Issued: 05/05/2015
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramanujam, Gopalan
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US13/683,012
• Publication Number:
  US 20130080742A1
• Time in Patent Office: 895 Days
• Field of Search: 708/204, 708550-553
• US Class Current: 708/204
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Claims

1. A system comprising:

a processor comprising

a register file including a first packed data register and a second packed data register,

a decoder to decode a first instruction,

scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution, and

execution logic coupled to the decoder and the scheduling logic,

wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed signed data elements to a plurality of unsigned results,

wherein the plurality of first packed signed data elements from the first packed data register is converted to the plurality of unsigned results, the unsigned results are saturated and stored in the second packed data register, and each of the first packed signed data elements has a first number of bits, each of the unsigned results has a second number of bits, and the second number of bits is one half the first number of bits; and

a memory controller coupled to the processor, wherein the memory controller is integral with the processor.

2. The system of claim 1, wherein the first number of bits is 32 and the second number of bits is 16.

3. The system of claim 1, wherein the first number of bits is 64 and the second number of bits is 32.

4. The system of claim 1, wherein the processor further comprises register renaming logic to associate physical registers with architectural registers.

5. A system comprising:

a processor comprising

a register file including a first packed data register and a second packed data register,

a decoder to decode a first instruction,

scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution, and

execution logic coupled to the decoder and the scheduling logic,

wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed integer data elements to a plurality of integer results,

wherein the plurality of first packed integer data elements from the first packed data register is converted to the plurality of integer results, the integer results are saturated and stored in the second packed data register, and each of the first packed integer data elements has a first number of bits, each of the integer results has a second number of bits, and the second number of bits is one half the first number of bits; and

a memory controller coupled to the processor, wherein the memory controller is integral with the processor.

6. The system of claim 5, wherein the first number of bits is 32 and the second number of bits is 16.

7. The system of claim 5, wherein the first number of bits is 64 and the second number of bits is 32.

8. The system of claim 5, wherein the processor further comprises register renaming logic to associate physical registers with architectural registers.