Source packet bridge

• US 9,026,680 B2
• Filed: 09/24/2012
• Issued: 05/05/2015
• Est. Priority Date: 07/02/2003
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hauck, Jerrold V.
• Primary Examiner(s): SHAW, PELING ANDREW
• Application Number:
  US13/625,798
• Publication Number:
  US 20130024593A1
• Time in Patent Office: 953 Days
• US Class Current: 709/249
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052

Abstract

A communication function between ports on a node that does not require a common time base to be distributed across the network is disclosed. A data stream received over a first port is placed on an interface between nodes using the time base of the first port; a second port samples the data stream on the interface and timestamps it using the time base of the second port. The data stream is timestamped by the second port and packetized before transmitted to the second node to another bridge or device. Alternatively, the first port extracts a time stamp from the data stream and calculates an offset using a cycle timer value from the bus connected to the first port. The offset is added to the cycle timer value on the bus connected to the second port and used to timestamp the data stream.

Claims

1. A method of implementing a source packet bridge on a network of nodes, the source packet bridge having a node with a first port, the first port having a first time base, a second port, the second port having a second time base, and an internal interface between the first port and the second port, where the first port is connected to a first link and the second port is connected to a second link, the first link associated with the first time base, the second link associated with the second time base, where the first time base and second time bases are different;

the method comprising;

extracting a first set of data blocks received from the first link via the first port according to the first time base;

storing the first set of data blocks within an internal FIFO (first in first out);

transmitting a second set of data blocks to the second link over the second port according to the second time base, the second set of data blocks comprising one or more data blocks retrieved from the internal FIFO; and

compensating for the difference between the first time base and the second time base by inserting one or more empty data blocks;

where at least one or more of the first or second set of data blocks are further encapsulated in packets;

where each packet exceeds a minimum number of data blocks per isochronous period.

2. The method of claim 1, where the first and second set of data blocks comprise isochronous data.

3. The method of claim 1, where the first and second set of data blocks comprise packets.

4. The method of claim 1, where each packet does not exceed a maximum number of data blocks per isochronous period.

5. The method of claim 1, where an average bandwidth into the first link and out of the second link is constant.

6. A source packet bridge apparatus comprising:

a first port, the first port configured to operate with a first time base;

a second port, the second port configured to operate with a second time base;

an internal interface between the first port and the second port, where the first port is connected to a first link and the second port is connected to a second link, the first link associated with the first time base, the second link associated with the second time base, where the first time base and second time bases are different;

a processor; and

a non-transitory computer readable storage medium with at least one computer program stored thereon, the at least one computer program configured to, when executed on the processor, cause the processor to;

extract a first set of data blocks received from the first link via the first port according to the first time base;

store the first set of data blocks within an internal FIFO (first in first out);

transmit a second set of data blocks to the second link over the second port according to the second time base, the second set of data blocks comprising one or more data blocks retrieved from the internal FIFO; and

compensate for the difference between the first time base and the second time base by insertion of one or more empty data blocks;

where at least one or more of the first or second set of data blocks are further encapsulated in packets;

where each packet exceeds a minimum number of data blocks per isochronous period.

7. The source packet bridge apparatus of claim 6, where the first and second set of data blocks comprise isochronous data.

8. The source packet bridge apparatus of claim 6, where the first and second links each comprise a high speed serial bus.

9. The source packet bridge apparatus of claim 8, where the extraction is configured to unpack the first set of data blocks from a first packet.

10. The source packet bridge apparatus of claim 9, where the transmission is configured to pack the second set of data blocks into a second packet.

11. The source packet bridge apparatus of claim 10, where at least one of the extraction and the transmission is configured to keep an average bandwidth out of the source packet bridge constant.

12. The source packet bridge apparatus of claim 10, where the first set of data blocks is stored according to an associated time stamp.

13. A source packet bridge apparatus comprising:

logic circuitry configured to extract a first set of data blocks received from a first link via a first port according to a first time base;

where the first set of data blocks is associated with one or more timestamps;

logic circuitry configured to store the first set of data blocks within an internal FIFO (first in first out);

logic circuitry configured to transmit a second set of data blocks to a second link over a second port according to a second time base without regard for the one or more timestamps where the first time base and second time bases are of different, the second set of data blocks comprising one or more data blocks retrieved from the internal FIFO; and

logic circuitry configured to compensate for the difference between the first time base and the second time base by insertion of one or more empty data blocks;

where the second set of data blocks are configured to be reconstructed at a receiver device according to the one or more timestamps;

where at least one or more of the first or second set of data blocks are further encapsulated in packets;

where each packet exceeds a minimum number of data blocks per isochronous period.

14. The source packet bridge apparatus of claim 13, where the first and second links each comprise a high speed serial bus.

15. The source packet bridge apparatus of claim 13, where the logic circuitry configured to extract is further configured to unpack the first set of data blocks from a first packet.

16. The source packet bridge apparatus of claim 13, where the logic circuitry configured to transmit is further configured to pack the second set of data blocks into a second packet.

17. The source packet bridge apparatus of claim 16, where the first and second set of data blocks comprise isochronous data.