Prefectching in PCI express

• US 9,026,682 B2
• Filed: 12/13/2012
• Issued: 05/05/2015
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Rosenbluth, Mark B., Bhatt, Ajay V., Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert G., Falik, Ohad, Mendelson, Avi, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron, Harriman, David J.
• Primary Examiner(s): Abad, Farley
• Assistant Examiner(s): MARTINEZ, DAVID E
• Application Number:
  US13/713,635
• Publication Number:
  US 20130132622A1
• Time in Patent Office: 873 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

an I/O element to;

receive a packet over an interconnect from a device, wherein the packet comprises a header and the header is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol;

identify a hint from a hint field in the header of the packet, wherein the header is to comprise at least four bytes, a byte zero of the header is to comprise a format field and a type field, a byte one of the header is to comprise the hint field, byte zero comprises the first of the at least four bytes, and byte one comprises the second of the at least four bytes, and the hint is to indicate an intended use of data in a memory associated with a transaction; and

initiate prefetching of the data based at least in part on the hint.

2. The apparatus of claim 1, wherein the interconnect comprises at least one of a physical layer, a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer, a physical layer including one or more protocols.

3. The apparatus of claim 1, wherein the interconnect comprises a PCIe-compliant interconnect.

4. The apparatus of claim 1, wherein the apparatus comprises a root controller and the root controller comprises transport layer logic.

5. The apparatus of claim 1, wherein the packet is associated with a first request of the memory and the prefetched data is utilized in a subsequent request of the memory.

6. The apparatus of claim 1, wherein the device is a selected one of a group of devices, the group consisting of:

a) a processing element;

b) a microprocessor;

c) a root controller;

d) a switch;

e) a controller hub;

f) a graphics accelerator; and

g) an input/output (I/O) device.

7. The apparatus of claim 1, wherein the transaction includes a read request of the memory.

8. The apparatus of claim 1, wherein the transaction includes a write request of the memory.

9. The apparatus of claim 1, wherein the transaction includes a request to read and write to the memory.

10. The apparatus of claim 1, wherein the packet includes a data payload.

11. The apparatus of claim 1, wherein the memory is identifiable from the hint.

12. The apparatus of claim 1, wherein the I/O module is further configured to prefetch the data.

13. An apparatus comprising:

an I/O module to;

generate a header of at least one packet of a transaction, wherein the header is compliant with a PCIe-based protocol and is to comprise at least four bytes, a byte zero of the header is to comprise a format field and a type field, a byte one of the header is to comprise a hint field to indicate a hint, byte zero comprises the first of the at least four bytes, and byte one comprises the second of the at least four bytes, and the hint indicates a potential future use of data in a memory associated with the transaction; and

send the packet to a device over an interconnect, wherein the device is to prefetch the data based at least in part on the hint.

14. The apparatus of claim 13, wherein the interconnect comprises at least one of a physical layer, a physical layer to support a PCIe protocol layer, and a physical layer including one or more protocols.

15. The apparatus of claim 13, wherein the interconnect comprises a PCIe-compliant interconnect.

16. The apparatus of claim 13, wherein the hint is included in a header of the packet.

17. The apparatus of claim 16, wherein the header includes a hint field indicating the presence of the hint in the packet.

18. The apparatus of claim 17, wherein the packet header further includes a data length field, and an attribute field.

19. The apparatus of claim 13, wherein the packet is associated with a request of the memory.

20. The apparatus of claim 13, wherein the request is one of a group comprising:

a) a read request of the memory;

b) a write request of the memory; and

c) a read and write request of the memory.

21. The apparatus of claim 13, wherein the transaction includes a first request and the I/O module is further configured to send a second request targeting the prefetched data.

22. An apparatus comprising:

a root controller to;

receive a packet from a device over an interconnect, wherein the root controller includes a protocol stack including a transaction layer, a link layer, and a physical layer, and the packet includes a transaction layer header, the transaction layer header is compliant with a PCIe-based protocol, the header is to comprise at least four bytes, a byte zero of the header is to comprise a format field and a type field, a byte one of the header is to comprise a hint field, byte zero is to comprise the first of the at least four bytes, and byte one is to comprise the second of the at least four bytes;

identify a hint from the hint field; and

initiate a prefetch of a data element based at least in part on the hint, wherein the packet is to indicate an amount of data to be prefetched and address information of prefetchable memory associated with the data element.

23. A method comprising:

receiving a packet over an interconnect from a device, wherein the packet comprises a header and the header is compliant with a PCIe-based protocol;

identifying a hint from a hint field in the header of the packet, wherein the header is to comprise at least four bytes, a byte zero of the header is to comprise a format field and a type field, a byte one of the header is to comprise the hint field, byte zero comprises the first of the at least four bytes, and byte one comprises the second of the at least four bytes, and the hint is to indicate an intended use of data in a memory associated with a transaction; and

initiating prefetching of the data based at least in part on the hint.

24. The method of claim 23, wherein initiating prefetching includes prefetching the data for potential access by a subsequent request.

25. The method of claim 23, wherein the intended use is not performed.

26. The method of claim 23, wherein the hint is included in a header of the packet included in the transaction.

27. The method of claim 26, wherein the header is a transaction layer header.

28. The method of claim 23, wherein the request is one of a group comprising:

a) a read request of the memory;

b) a write request of the memory; and

c) a read and write request of the memory.

29. A system comprising:

a first computing device;

a second computing device to;

receive a packet over an interconnect from the first device, wherein the packet comprises a header and the header is compliant with a PCIe-based protocol;

identify a hint from the header of the packet, wherein the header is to comprise at least four bytes, a byte zero of the header is to comprise a format field and a type field, a byte one of the header is to comprise the hint field, byte zero comprises the first of the at least four bytes, and byte one comprises the second of the at least four bytes, and the hint is to indicate an intended use of data in a memory associated with a transaction; and

initiate prefetching of the data based at least in part on the hint.

30. The system of claim 29, wherein the second computing device is further configured to prefetch the data based at least in part on the hint.

31. The system of claim 29, wherein the first computing device is communicatively coupled to the second computing device using the interconnect.

32. The system of claim 29, further comprising the second device, wherein the first device includes a Universal Serial Bus (USB) device and the second device includes a microcontroller.

33. The system of claim 29, wherein the first device includes an interconnect controller hub.

34. The system of claim 29, wherein the first device includes a first microcontroller and the second device includes a second microcontroller.

35. An apparatus comprising:

an I/O module to;

generate a packet in a transaction, the packet including a packet header and a payload, wherein the packet header is compliant with a PCIe-based protocol and is to comprise at least four bytes, a byte zero of the header is to comprise a format field and a type field, a byte one of the header is to comprise a hint field to indicate a hint, byte zero comprises the first of the at least four bytes, byte one comprises the second of the at least four bytes, and the hint is to indicate an intended use of data in a memory associated with the transaction; and

cause the packet to be sent to a device over an interconnect.