Intelligent monitoring for computation in memory

• US 9,026,719 B2
• Filed: 11/15/2012
• Issued: 05/05/2015
• Est. Priority Date: 11/15/2012
• Status: Expired due to Fees

• Current Assignee: Elwha LLC (Intellectual Ventures LLC)
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Hyde, Roderick A., Pasch, Nicholas F., Tegreene, Clarence T.
• Primary Examiner(s): NGUYEN, HIEP T
• Application Number:
  US13/678,430
• Publication Number:
  US 20140136754A1
• Time in Patent Office: 901 Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information

Abstract

A memory device can include a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to selectively distribute functionality across the non-volatile memory array.

Claims

1. A memory device comprising:

a memory integrated circuit chip including at least;

a non-volatile memory array including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

control logic including one or more logic layers integrated in combination with the one or more layers of discrete storage cells and distributed extending laterally over the non-volatile memory array, the control logic operable to selectively distribute information processing functionality across the non-volatile memory array.

2. The memory device according to claim 1 further comprising:

a bus integrated with the control logic and the non-volatile memory array on the memory integrated circuit chip.

3. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor a history and pattern of memory accesses in the non-volatile memory array and perform sorting of information stored in the non-volatile memory array during system idle based at least in part on the history and pattern of the memory accesses.

4. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor memory accesses and perform pattern recognition of the monitored memory accesses.

5. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor memory accesses, determine statistics on type and number of instructions of the monitored memory accesses, and predict a sequence of instructions and data at least in part by using the determined statistics.

6. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor memory accesses, detect a pattern of instructions and data from the monitored memory accesses, predict expected instructions and data from the detected pattern of instructions and data, and preprocessing the predicted expected instructions.

7. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to perform selective memory access and management operations independently of signals external to the memory device.

8. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor operating characteristics of the memory device, analyze the monitored operating characteristics, detect a precursor to a memory failure based on the analysis, and allocate memory accesses based at least in part on the detected precursor.

9. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory elements; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor writes to the plurality of memory elements of the non-volatile memory array and allocate writes to the plurality of memory elements based at least in part on results of the monitoring.

10. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory elements; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor writes to the plurality of memory elements of the non-volatile memory array and distribute writes across the plurality of memory elements based at least in part on results of the monitoring.

11. The memory device according to claim 1 wherein:

the non-volatile memory array is partitioned into a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is partitioned into a plurality of command logic blocks spatially distributed over the non-volatile memory array wherein one or more of the plurality of command logic blocks are associated with one or more of the plurality of memory blocks.

12. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks characterized by a plurality of different operating characteristics, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to selectively distribute functionality over the plurality of memory blocks.

13. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks characterized by a plurality of different operating characteristics, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to analyze memory accesses and selectively distribute functionality over the plurality of memory blocks based on the analysis.

14. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks characterized by a plurality of different operating characteristics, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to analyze memory accesses, determine application constraints based on the analysis, and selectively distribute functionality over the plurality of memory blocks based at least in part on the determined application constraints.

15. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks characterized by a plurality of different Quality-of-Service (QoS) ratings, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to analyze memory accesses, determine priority of performance based on the analysis, and selectively distribute functionality over the plurality of memory blocks based at least in part on the determined priority of performance.

16. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks characterized by a plurality of different Quality-of-Service (QoS) ratings, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to analyze memory accesses, perform error detection based on the analysis, and characterize Quality-of-Service (QoS) ratings of the plurality of memory blocks based at least in part on the performed error detection.

17. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor writes to the plurality of memory blocks of the non-volatile memory array and allocate writes to the memory blocks based at least in part on results of the monitoring.

18. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor operating characteristics of the memory device, analyze the monitored operating characteristics, detect a precursor to a memory failure based on the analysis, and allocate memory accesses among the plurality of memory blocks based at least in part on the detected precursor.

19. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to receive a report on an operating condition of system performance for a system including the memory device at system bootstrap loading and allocate information processing functionality among the plurality of memory blocks based at least in part on the report.

20. The memory device according to claim 1 wherein:

at least one sensor operable to detect an operating condition of a system including the memory device, wherein;

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor the operating condition, analyze the monitored operating condition, detect a precursor to a memory failure based on the analysis, and allocate memory accesses among the plurality of memory blocks based at least in part on the detected precursor.

21. The memory device according to claim 1 wherein:

at least one sensor operable to detect an operating condition of a system including the memory device, wherein;

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor the operating condition, monitor memory accesses, analyze the monitored operating conditions and memory accesses, predict expected outcomes based at least in part on the monitored operating conditions and memory accesses, and allocate memory accesses based on the predicted expected outcomes.

22. The memory device according to claim 1 wherein:

at least one sensor operable to detect an operating condition of a system including the memory device, wherein;

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor the operating condition, monitor memory accesses, analyze the monitored operating conditions and memory accesses, predict expected outcomes based at least in part on the monitored operating conditions and memory accesses, and allocate memory accesses to the plurality of memory blocks based at least in part on the predicted expected outcomes.

23. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks characterized by a plurality of different operating characteristics, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to perform a plurality of error correction algorithms and selectively allocate one or more of the plurality of error correction algorithms to one or more of the plurality of memory blocks.

24. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to access a time signal and monitor memory accesses referenced by the time signal, analyze workload based at least in part on the monitored memory accesses, and allocate memory accesses among the plurality of memory blocks based at least in part on the analyzed workload.

25. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks including at least one memory block including lossy memory, the plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor memory accesses, analyze the memory accesses to determine instructions and data indicative for storage in the at least one memory block including lossy memory, and selectively allocate memory accesses to the at least one memory block including lossy memory.

26. The memory device according to claim 1 wherein:

the non-volatile memory array includes a plurality of memory blocks including one or more layers of discrete storage cells extending laterally across the memory integrated circuit chip; and

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to selectively access one or more of the plurality of memory blocks as bit-mapped memory and access one or more of the plurality of memory blocks as vector memory.

27. The memory device according to claim 1 further comprising:

a communication interface coupled to the non-volatile memory array and the control logic, the communication interface operable to communicate external to the memory device.

28. The memory device according to claim 1 further comprising:

optical silicon integrated with the control logic and the non-volatile memory array on the memory integrated circuit chip and operable to communicate optically, independently of a bus coupled to the memory device wherein the control logic is operable to receive functions for tracking applications and processes independently of communication via the bus.

29. The memory device according to claim 1 wherein:

the control logic operable to selectively distribute information processing functionality across the non-volatile memory array is operable to monitor memory accesses and perform pattern recognition of the monitored memory accesses operable in combination with the non-volatile memory array to accumulate information about a product.

30. A memory system comprising:

means for storing information in a memory device including a non-volatile memory array including one or more layers of discrete storage cells extending laterally across a memory integrated circuit chip;

means for controlling the means for storing information, the means for controlling integrated with and distributed over the non-volatile memory array in combination with the one or more layers of discrete storage cells and distributed extending laterally over the non-volatile memory array; and

means for selectively distributing information processing functionality across the non-volatile memory array.

31. A system comprising:

circuitry for storing information in a memory device including a non-volatile memory array including one or more layers of discrete storage cells extending laterally across a memory integrated circuit chip;

circuitry for controlling the means for storing information, the circuitry for controlling integrated with and distributed over the non-volatile memory array in combination with the one or more layers of discrete storage cells and distributed extending laterally over the non-volatile memory array; and

circuitry for selectively distributing information processing functionality across the non-volatile memory array.