Signal control device and signal control method
First Claim
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1. A signal control device comprising:
- a dual port random access memory (RAM), wherein data signals are read from the dual port RAM by a first central processing unit (CPU) and written to the dual port RAM by a second CPU at predetermined operation timings, wherein the first CPU and the second CPU are connected to two ports of the dual port RAM;
an address collision detection unit which detects collision between an address from which the first CPU reads a data signal from the dual port RAM and an address in which the second CPU writes a data signal to the dual port RAM;
a first storage unit which stores the data signal which the first CPU reads from the dual port RAM;
a second storage unit which stores the data signal read from the address in which the second CPU writes the data signal to the dual port RAM, wherein the second storage unit stores the data signal irrespective of whether the second CPU is in a write enable state when the collision between the addresses is detected and the first CPU is not in a read enable state; and
a switching unit, located outside of the dual port RAM, that switches a reading source that outputs the data signal to the port to which the first CPU is connected, wherein the switching unitreads the data signal from the first storage unit and outputs the read data signal from the first storage unit to the first CPU, when the collision between the addresses is not detected and the first CPU is in the read enable state,reads the data signal from the first storage unit when the collision between the addresses is detected, the first CPU is not in the read enable state, and the second CPU is not in the write enable state, wherein the switching unit outputs the read data signal from the first storage unit to the first CPU when the first CPU enters the read enable state, andreads the data signal from the second storage unit when the collision between the addresses is detected, the first CPU is not in the read enable state, and the second CPU is in the write enable state, wherein the switching unit outputs the read data signal from the second storage unit to the first CPU when the first CPU enters the read enable state.
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Abstract
A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively; an address collision detection unit detecting collision between addresses in which the first and second CPUs respectively read and write the data signal from and to the dual port RAM; a first storage unit storing the data signal read by the first CPU; a second storage unit storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM when the collision between the addresses is detected; and a switching unit switching a reading source outputting the data signal to the port to which the first CPU is connected and outputting the read data signal to the first CPU entering a readable state.
44 Citations
11 Claims
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1. A signal control device comprising:
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a dual port random access memory (RAM), wherein data signals are read from the dual port RAM by a first central processing unit (CPU) and written to the dual port RAM by a second CPU at predetermined operation timings, wherein the first CPU and the second CPU are connected to two ports of the dual port RAM; an address collision detection unit which detects collision between an address from which the first CPU reads a data signal from the dual port RAM and an address in which the second CPU writes a data signal to the dual port RAM; a first storage unit which stores the data signal which the first CPU reads from the dual port RAM; a second storage unit which stores the data signal read from the address in which the second CPU writes the data signal to the dual port RAM, wherein the second storage unit stores the data signal irrespective of whether the second CPU is in a write enable state when the collision between the addresses is detected and the first CPU is not in a read enable state; and a switching unit, located outside of the dual port RAM, that switches a reading source that outputs the data signal to the port to which the first CPU is connected, wherein the switching unit reads the data signal from the first storage unit and outputs the read data signal from the first storage unit to the first CPU, when the collision between the addresses is not detected and the first CPU is in the read enable state, reads the data signal from the first storage unit when the collision between the addresses is detected, the first CPU is not in the read enable state, and the second CPU is not in the write enable state, wherein the switching unit outputs the read data signal from the first storage unit to the first CPU when the first CPU enters the read enable state, and reads the data signal from the second storage unit when the collision between the addresses is detected, the first CPU is not in the read enable state, and the second CPU is in the write enable state, wherein the switching unit outputs the read data signal from the second storage unit to the first CPU when the first CPU enters the read enable state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11)
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8. A signal control method comprising:
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detecting collision between an address from which a first central processing unit (CPU) reads a data signal from a dual port random access memory (RAM) and an address in which a second CPU writes a data signal to the dual port RAM, wherein the data signals are read from and written in the dual port RAM at predetermined operation timings by the first CPU and the second CPU connected to two ports of the dual port RAM, respectively; storing the data signal which the first CPU reads from the dual port RAM in a first storage unit; storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM in a second storage unit, wherein the data signal is stored irrespective of whether the second CPU is in a write enable state when the collision between the addresses is detected and the first CPU is not in a read enable state; and switching a reading source that outputs the data signal to the port to which the first CPU is connected, wherein the switching of the reading source comprises; reading the data signal from the first storage unit and outputting the read data signal from the first storage unit to the first CPU when the collision between the addresses is not detected and the first CPU is in the read enable state, reading the data signal from the first storage unit when the collision between the addresses is detected, the first CPU is not in the read enable state, and the second CPU is not in the write enable state, wherein the read data signal is outputted from the first storage unit to the first CPU when the first CPU enters the read enable state, and reading the data signal from the second storage unit when the collision between the addresses is detected, the first CPU is not in the read enable state, and the second CPU is in the write enable state, wherein the read data signal from the second storage unit is outputted to the first CPU when the first CPU enters the read enable state, and wherein the switching is performed outside of the dual port RAM.
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Specification
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Current AssigneeSony Corporation (Sony Group Corp.)
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Original AssigneeSony Corporation (Sony Group Corp.)
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InventorsTanaka, Shinjiro
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Primary Examiner(s)Thai, Tuan
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Assistant Examiner(s)Chappell, Daniel C
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Application NumberUS13/066,266Publication NumberTime in Patent Office1,485 DaysField of SearchNoneUS Class Current711/149CPC Class CodesG06F 13/16 for access to memory bus G0...G06F 15/167 using a common memory, e.g....G11C 29/818 for dual-port memoriesG11C 7/1075 for multiport memories each...
