Detecting and reissuing of loop instructions in reorder structure

• US 9,026,769 B1
• Filed: 01/24/2012
• Issued: 05/05/2015
• Est. Priority Date: 01/31/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Jamil, Sujat, O'Bleness, R. Frank, Delgross, Joseph, Hameenanttila, Tom
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US13/357,567
• Time in Patent Office: 1,197 Days
• Field of Search: 712/241, 712/E9.078, 712/E9.058
• US Class Current: 712/241
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags

Abstract

A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.

Claims

1. A method comprising:

storing, according to program order, decoded instructions including instructions that form a loop in an instruction reorder structure;

issuing the decoded instructions from the instruction reorder structure for execution out of program order;

detecting the loop in the decoded instructions stored in the instruction reorder structure; and

reissuing the instructions that form the loop from the instruction reorder structure for re-execution.

2. The method of claim 1, wherein detecting the loop in the decoded instructions stored in the instruction reorder structure comprises:

receiving a result of an executed instruction from an execution unit;

determining that an address of the result occurs earlier than an address of the executed instruction; and

determining that an instruction associated with the address of the result is stored in the instruction reorder structure.

3. The method of claim 1, further comprising:

disabling a component that provides instructions to the instruction reorder structure while loop instructions are re-executed from the instruction reorder structure.

4. The method of claim 3, further comprising:

detecting the loop has been exited; and

re-enabling the component.

5. The method of claim 4, wherein detecting the loop has been exited comprises:

receiving a result of an executed instruction from an execution unit; and

determining that an address of the result is associated with a next sequential instruction following the executed instruction in program order.

6. The method of claim 4, wherein detecting the loop has been exited comprises:

determining from a loop instruction a number of iterations of the loop;

decrementing the number of iterations upon completion of each loop iteration; and

detecting the loop has been exited when the number of iterations reaches zero.

7. The method of claim 1, further comprising:

storing execution results in the instruction reorder structure; and

writing the execution results from the instruction reorder structure into a register file according to program order.

8. An apparatus comprising:

an instruction reorder structure configured to

store decoded instructions including instructions that form a loop according to program order, and

issue the decoded instructions for execution out of program order; and

a loop processing controller configured to detect the loop in the decoded instructions stored in the instruction reorder structure, and cause the instruction reorder structure to reissue the instructions that form the loop for re-execution.

9. The apparatus of claim 8, wherein the loop processing controller is further configured to disable one or more components during re-execution of loop instructions from the instruction reorder structure.

10. The apparatus of claim 8, wherein the loop processing controller is further configured to detect that the loop has been exited.

11. The apparatus of claim 8, wherein the loop processing controller is further configured to determine a number of instructions in the loop and a number of iterations of the loop.

12. The apparatus of claim 8, wherein the instruction reorder structure is further configured to store execution results and write the execution results into a register file according to program order.

13. The apparatus of claim 8, wherein the instruction reorder structure includes a plurality of storage locations, and each of the storage locations is configured to store one decoded instruction.

14. The apparatus of claim 13, wherein each of the storage locations includes a bit, and the loop processing controller is further configured to set the bit of each storage location associated with each loop instruction to indicate that the decoded instruction stored in the storage location is to be re-executed.

15. A system comprising:

an instruction cache configured to receive instructions from main memory;

instruction fetch circuitry configured to fetch the instructions from the instruction cache;

instruction decode circuitry configured to receive and decode the instructions from the instruction fetch circuitry;

an instruction reorder structure configured to

store decoded instructions including instructions that form a loop according to program order, and

issue the decoded instructions for execution out of program order; and

a loop processing controller configured to detect the loop in the decoded instructions stored in the instruction reorder structure, and cause the instruction reorder structure to reissue the instructions that form the loop for re-execution.

16. The system of claim 15, further comprising execution circuitry configured to:

receive the decoded instructions from the instruction reorder structure;

execute the decoded instructions; and

convey an execution result associated with the decoded instruction to the instruction reorder structure.

17. The system of claim 15, further comprising:

a register file configured to receive an execution result from the instruction reorder structure according to program order.

18. The system of claim 15, wherein the instruction cache is disabled during execution of loop instructions from the instruction reorder structure.

19. The system of claim 18, wherein the instruction cache is disabled by causing a clock signal value provided to the instruction cache to remain constant.

20. The system of claim 18, wherein the instruction cache is disabled by adjusting a voltage supplied to the instruction cache.