Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor
First Claim
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1. A method comprising:
- determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, the non-core domain including at least one graphics engine;
responsive to the determination, sending a request from the non-core domain to a power controller of the multi-domain processor to reduce a frequency of a core domain of the multi-domain processor, the core domain including at least one core; and
responsive to the request, reducing the frequency of the core domain.
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Abstract
In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
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Citations
21 Claims
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1. A method comprising:
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determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, the non-core domain including at least one graphics engine; responsive to the determination, sending a request from the non-core domain to a power controller of the multi-domain processor to reduce a frequency of a core domain of the multi-domain processor, the core domain including at least one core; and responsive to the request, reducing the frequency of the core domain. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A processor comprising:
a core domain having one or more cores, at least one non-core domain having at least one graphics engine, and a power controller, the core domain to operate at a frequency range between a maximum frequency and a guaranteed frequency, the maximum frequency and the guaranteed frequency set at manufacture, wherein the non-core domain is to cause the power controller to dynamically reduce at least one of the maximum frequency and the guaranteed frequency of the core domain. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A system comprising:
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a multi-domain processor including a core domain, at least one non-core domain, and a power controller, the core domain to operate at a frequency range between a maximum frequency and a guaranteed frequency, the maximum frequency and the guaranteed frequency set at manufacture, wherein the power controller includes a configuration register accessible to the non-core domain, the configuration register to store at least one value to be written by a driver of the non-core domain to enable a dynamic reduction in a frequency range at which the core domain can operate; and a dynamic random access memory (DRAM) coupled to the multi-domain processor. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification