Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory

• US 9,026,867 B1
• Filed: 03/15/2013
• Issued: 05/05/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Northcott, Philip Lyon, Graumann, Peter, Bates, Stephen
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US13/844,499
• Time in Patent Office: 781 Days
• Field of Search: 714/763, 714/773, 714/704, 365/185.09, 365/185.33
• US Class Current: 714/704
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Claims

1. An electronically-implemented method of adapting to changing characteristics of multi-level flash cells, the method comprising:

storing data in pages of a memory device having multi-level cells, wherein two or more bonded pages share a set of multi-level cells, wherein a multi-level cell is configured to store a first bit for a first page and a second bit for a second page of the bonded pages;

arranging the pages of the memory device into a plurality of page stripes for storage of data,

wherein page stripes individually comprise one or more pages or integer fractions thereof,

wherein the bonded pages belong to separate page stripes such that a first page stripe and a second page stripe of a bonded page stripe are related by having bonded pages of memory that share multi-level cells,

wherein an ECC characteristic is selected for a page stripe and is applicable to the one or more pages or integer fractions thereof of the page stripe,

wherein the plurality of page stripes include at least a third page stripe associated with a first gear such that the third page stripe has a first non-zero integer journaling cell slot capacity for data and a first capacity for parity bits of a first error correction code protective of data stored within the first page stripe and a fourth page stripe associated with a second gear such that the fourth page stripe has a second non-zero integer journaling cell slot capacity different from the first non-zero journaling slot capacity and a second capacity for parity bits of the first error correction code protective of data stored within the second page stripe;

using the first page stripe and the second page stripe of the bonded page stripe to store data;

determining a first estimated bit error rate (first BER) for the first page stripe and a second estimated bit error rate (second BER) for the second page stripe during field use of the memory device, wherein none of the first page stripe or the second page stripe is associated with gear zero at the time of determining the first BER and the second BER, wherein gear zero corresponds to a zero journaling cell slot capacity; and

when at least one of the first BER or the second BER exceeds a first predetermined threshold, associating gear zero with a selected one of the first page stripe or the second page stripe.

2. The method of claim 1, wherein the second page stripe corresponds to the selected one of the first page stripe or the second page stripe for association with gear zero, the method further comprising:

performing a data integrity test on the first page stripe to determine a new estimated bit error rate after the association with gear zero for the second page stripe; and

selecting from at least the first gear, the second gear, or gear zero for association with the first page stripe based on the new estimated bit error rate.

3. The method of claim 2, further comprising increasing a journaling cell slot capacity of the first page stripe over a previously assigned journaling cell slot capacity.

4. The method of claim 2, wherein performing the data integrity test comprises retaining a previous gear setting for the first page stripe and monitoring a number of bit errors corrected on the first page stripe during field use.

5. The method of claim 1, wherein when at least one of the first BER or the second BER exceeds the first predetermined threshold, the method further comprises selecting the first page stripe or the second page stripe having the worse estimated bit error rate for association with gear zero.

6. The method of claim 1, wherein page stripes individually comprise four or more pages.

8. The method of claim 1, wherein when at least one of the first BER, the second BER, or the third BER exceeds the first predetermined threshold, the method further comprises selecting the first page stripe, the second page stripe, or the third page stripe having the worst bit error rate for association with gear zero.

9. The method of claim 1, wherein the third page stripe corresponds to the selected one of the first page stripe, the second page stripe, or the third page stripe, for association with gear zero, the method further comprising:

performing a data integrity test on the first page stripe to determine a fourth estimated bit error rate (fourth BER) for the first page stripe and on the second page stripe to determine a fifth estimated bit error rate (fifth BER) for the second page stripe after the association with gear zero for the third page stripe;

selecting from at least the first gear, the second gear, or gear zero for association with the first page stripe based on the fourth BER; and

selecting from at least the first gear, the second gear, or gear zero for association with the second page stripe based on the fifth BER.

10. The method of claim 9, wherein when at least one of the fourth BER or the fifth BER exceeds the second predetermined threshold, the method further comprises selecting the first page stripe or the second page stripe having the worse estimated bit error rate for association with gear zero.

7. An electronically-implemented method of selecting an error correction code (ECC) characteristic, the method comprising:

storing data in pages of a memory device having multi-level cells, wherein two or more bonded pages share a set of physical cells, wherein a multi-level cell is configured to store a first bit for a first page, a second bit for a second page, and a third bit for a third page of the bonded pages;

arranging the pages of the memory device into a plurality of page stripes for storage of data,

wherein page stripes individually comprise one or more pages or integer fractions thereof,

wherein the bonded pages belong to separate page stripes such that a first page stripe, a second page stripe, and a third page stripe of a bonded page stripe are related by having bonded pages of memory that share multi-level cells,

wherein an ECC characteristic is selected for a page stripe and is applicable to the pages of the page stripe,

wherein the plurality of page stripes include at least a fourth page stripe associated with a first gear such that the fourth page stripe has a first non-zero integer journaling cell slot capacity for data and a first capacity for parity bits of a first error correction code protective of data stored within the first page stripe, and a fifth page stripe associated with a second gear such that the second page stripe has a second non-zero integer journaling cell slot capacity different from the first non-zero journaling slot capacity and a second capacity for parity bits of the first error correction code protective of data stored within the second page stripe;

using the first page stripe, the second page stripe, and the third page stripe of the bonded page stripe to store data;

determining a first estimated bit error rate (first BER) for the first page stripe, a second estimated bit error rate (second BER) for the second page stripe, and a third estimated bit error rate (third BER) for the third page stripe during field use of the memory device, wherein none of the first page stripe, the second page stripe, or the third page stripe is associated with gear zero at the time of determining the first BER, the second BER, and the third BER, wherein gear zero corresponds to a zero journaling cell slot capacity; and

when at least one of the first BER, the second BER, or the third BER exceeds a first predetermined threshold, associating gear zero with a selected one of the first page stripe, the second page stripe, or the third page stripe.

11. An apparatus comprising:

a journaling engine configured to;

store data in pages of a memory device having multi-level cells, wherein two or more bonded pages share a set of multi-level cells, wherein a multi-level cell is configured to store a first bit for a first page and a second bit for a second page of the bonded pages;

arrange the pages of the memory device into a plurality of page stripes for storage of data,

wherein page stripes individually comprise one or more pages or integer fractions thereof,

wherein the bonded pages belong to separate page stripes such that a first page stripe and a second page stripe of a bonded page stripe are related by having bonded pages of memory that share multi-level cells,

wherein an error correction code (ECC) characteristic is selected for a page stripe and is applicable to the one or more pages or integer fractions thereof of the page stripe,

wherein the plurality of page stripes include at least a third page stripe associated with a first gear such that the third page stripe has a first non-zero integer journaling cell slot capacity for data and a first capacity for parity bits of a first error correction code protective of data stored within the first page stripe and a fourth page stripe associated with a second gear such that the fourth page stripe has a second non-zero integer journaling cell slot capacity different from the first non-zero journaling slot capacity and a second capacity for parity bits of the first error correction code protective of data stored within the second page stripe;

use the first page stripe and the second page stripe of the bonded page stripe to store data; and

an ECC encoder/decoder configured to;

determine a first estimated bit error rate (first BER) for the first page stripe and a second estimated bit error rate (second BER) for the second page stripe during field use of the memory device, wherein none of the first page stripe or the second page stripe is associated with gear zero at the time of determining the first BER and the second BER, wherein gear zero corresponds to a zero journaling cell slot capacity; and

when at least one of the first BER or the second BER exceeds a first predetermined threshold, associate gear zero with a selected one of the first page stripe or the second page stripe.

12. The apparatus of claim 11, wherein the second page stripe corresponds to the selected one of the first page stripe or the second page stripe for association with gear zero, wherein the ECC encoder/decoder is further configured to:

perform a data integrity test on the first page stripe to determine a new estimated bit error rate after the association with gear zero for the second page stripe; and

select from at least the first gear, the second gear, or gear zero for association with the first page stripe based on the new estimated bit error rate.

13. The apparatus of claim 12, wherein the ECC encoder/decoder is further configured to increase a journaling cell slot capacity of the first page stripe over a previously assigned journaling cell slot capacity.

14. The apparatus of claim 12, wherein to perform the data integrity test, the ECC encoder/decoder is further configured to retain a previous gear setting for the first page stripe and monitor a number of bit errors corrected on the first page stripe during field use.

15. The apparatus of claim 11, wherein when at least one of the first BER or the second BER exceeds the first predetermined threshold, the ECC encoder/decoder is further configured to select the first page stripe or the second page stripe having the worse estimated bit error rate for association with gear zero.

16. The apparatus of claim 11, wherein page stripes individually comprise four or more pages.

18. The apparatus of claim 11, wherein when at least one of the first BER, the second BER, or the third BER exceeds the first predetermined threshold, the ECC encoder/decoder is further configured to select the first page stripe, the second page stripe, or the third page stripe having the worst bit error rate for association with gear zero.

19. The apparatus of claim 11, wherein the third page stripe corresponds to the selected one of the first page stripe, the second page stripe, or the third page stripe, for association with gear zero, wherein:

the first circuit is further configured to perform a data integrity test on the first page stripe to determine a fourth estimated bit error rate (fourth BER) for the first page stripe and on the second page stripe to determine a fifth estimated bit error rate (fifth BER) for the second page stripe after the association with gear zero for the third page stripe;

the second circuit is further configured to select from at least the first gear, the second gear, or gear zero for association with the first page stripe based on the fourth BER; and

the second circuit is further configured to select from at least the first gear, the second gear, or gear zero for association with the second page stripe based on the fifth BER.

20. The apparatus of claim 19, wherein when at least one of the fourth BER or the fifth BER exceeds the second predetermined threshold, the second circuit is further configured to select the first page stripe or the second page stripe having the worse estimated bit error rate for association with gear zero.

17. An apparatus comprising:

a journaling engine configured to;

store data in pages of a memory device having multi-level cells, wherein two or more bonded pages share a set of physical cells, wherein a multi-level cell is configured to store a first bit for a first page, a second bit for a second page, and a third bit for a third page of the bonded pages;

arrange the pages of the memory device into a plurality of page stripes for storage of data,

wherein page stripes individually comprise one or more pages or integer fractions thereof,

wherein the bonded pages belong to separate page stripes such that a first page stripe, a second page stripe, and a third page stripe of a bonded page stripe are related by having bonded pages of memory that share multi-level cells,

wherein an error correction code (ECC) characteristic is selected for a page stripe and is applicable to the pages of the page stripe,

wherein the plurality of page stripes include at least a fourth page stripe associated with a first gear such that the fourth page stripe has a first non-zero integer journaling cell slot capacity for data and a first capacity for parity bits of a first error correction code protective of data stored within the first page stripe, and a fifth page stripe associated with a second gear such that the second page stripe has a second non-zero integer journaling cell slot capacity different from the first non-zero journaling slot capacity and a second capacity for parity bits of the first error correction code protective of data stored within the second page stripe;

use the first page stripe, the second page stripe, and the third page stripe of the bonded page stripe to store data;

a first circuit configured to determine a first estimated bit error rate (first BER) for the first page stripe, a second estimated bit error rate (second BER) for the second page stripe, and a third estimated bit error rate (third BER) for the third page stripe during field use of the memory device, wherein none of the first page stripe, the second page stripe, or the third page stripe is associated with gear zero at the time of determining the first BER, the second BER, and the third BER, wherein gear zero corresponds to a zero journaling cell slot capacity; and

a second circuit configured to associate gear zero with a selected one of the first page stripe, the second page stripe, or the third page stripe when at least one of the first BER, the second BER, or the third BER exceeds a first predetermined threshold.