Surface topography enhanced pattern (STEP) matching

• US 9,026,954 B2
• Filed: 01/17/2014
• Issued: 05/05/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Katakamsetty, Ushasree, Perez, Valerio Barnedo, Yeo, Wee Kwong
• Primary Examiner(s): Ngo, Brian
• Application Number:
  US14/157,530
• Publication Number:
  US 20140282292A1
• Time in Patent Office: 473 Days
• Field of Search: 716/51, 716/52, 716/53, 716/54
• US Class Current: 716/52
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC.

Claims

1. A process for enhancing a design file for generating a mask set having a plurality of masks used in lithographic processes to form a semiconductor device on a wafer, the process comprising:

processing a design data file, the design data file comprises information of design layers, wherein a design layer is used for generating a mask of the mask set, the information includes patterns of the design layers, wherein processing the design data file comprises

analyzing using a topography analysis module, the patterns of the design layers of the design data file comprising

performing a first analysis, wherein the first analysis comprises a topography analysis to determine accumulated topography information, wherein accumulated topography information comprises topography information of wafer which includes underlying topography information of the wafer processed by masks of underlying design layers, wherein regions of design layers are categorized according to a topography classification which is based on topographical height in each region relative to a baseline height, and

performing a second analysis, wherein the second analysis comprises a pattern analysis which comprises matching patterns of the masks to base patterns;

wherein matching patterns comprises classifying the matched patterns based on the topography profile, wherein the matched pattern is assigned a weight value according to type of topography profile or region and

enhancing using a pattern enhancement module, patterns of the design layers in the design data file based on the first and second analyses.

2. The process of claim 1 wherein the topography analysis comprises performing a simulation using a chemical mechanical polishing (CMP) model to generate topography profile for the device on the wafer which is processed by different mask levels.

3. The process of claim 2 comprising generating heat maps for each simulated mask levels, wherein the heat map is a color-coded map of the device based on the topography classification.

4. The process of claim 2 wherein the base patterns comprise known problem patterns or lithographic weak points.

5. The process of claim 2 comprising storing information related to a matched file, wherein the information comprises type of patterns of a design layer which match the base patterns and location of the patterns in its x-y coordinates on the device.

6. A process for enhancing a design file for generating a mask set having a plurality of masks used in lithography to form an integrated circuit (IC) on a wafer comprising:

processing a design data file, the design data file comprises information of design layers, the information includes patterns of the design layers, wherein processing the design data file comprises

analyzing using a topography analysis module, the design data file, wherein analyzing comprises

performing a first analysis, wherein the first analysis comprises a topography analysis to determine accumulated topography information of the design layers or mask levels of the IC, wherein regions on the IC of mask levels are categorized according to a topography classification which is based on topographical height in each region relative to a baseline height, and

performing a second analysis, wherein the second analysis comprises a pattern analysis which comprises matching patterns of the mask to base patterns;

storing information related to a matched file, wherein the information comprises type of patterns of a design layer which match the base patterns and location of the patterns in its x-y coordinates on the IC; and

enhancing using a pattern enhancement module, matched patterns in the design data file, wherein the step of enhancing comprises

classifying the matched patterns based on the topography profile, wherein a matched pattern is assigned a weight value according to type of topography profile or region; and

fixing the matched patterns based on enhancement priority rules, wherein the enhancement priority rules depend on type of pattern and the weight value.

7. The process of claim 6 wherein topography region which is a high region is assigned with a higher weight value relative to topography region which is a low region.

8. The process of claim 7 wherein the enhancement priority rules are defined in that higher priority is given to a matched pattern with higher weight value.

9. The process of claim 6 comprising generating an enhanced design data file after the step of enhancing the patterns.

10. The process of claim 9 wherein the step of enhancing the patterns is performed by a first party and the enhanced design data file is used to generate the mask set which is used by a second party for device fabrication.

11. The process of claim 10 wherein the first party comprises a device designer and the second party comprises a foundry.

12. A method of forming an integrated circuit device comprising:

providing a wafer having a substrate prepared with a photoresist layer;

processing the photoresist layer by passing a radiation from an exposure source of a lithography tool through a mask of a mask set generated based on a modified design data file, wherein the modified design data file comprises

a design data file that is processed and analyzed using a topography analysis module, the design data file includes a modified artwork file of a device, wherein the file comprises design data for patterns of mask levels, and patterns in the design data file are enhanced or modified based on analysis comprising

a first analysis, wherein the first analysis comprises a topography analysis to determine accumulated topography information, wherein accumulated topography information comprises topography information of wafer which includes underlying topography information of the wafer processed by masks of underlying design layers, wherein regions of design layers are categorized according to a topography classification which is based on topographical height in each region relative to a baseline height, and

a second analysis, wherein the second analysis comprises a pattern analysis which comprises matching patterns of the masks to base patterns wherein matching patterns comprises classifying the matched patterns based on the topography profile, wherein the matched pattern is assigned a weight value according to type of topography profile or region; and

developing the photoresist layer to transfer pattern on the mask set to the photoresist layer.

13. A process for modifying a design file for lithography comprising:

providing a design data file using a computer, the design data file comprises information for patterns of design layers in an integrated circuit (IC);

enhancing using a pattern enhancement module, patterns in the design data file based on an analysis, wherein the analysis using a topography analysis module, comprises

a first analysis, wherein the first analysis comprises a topography analysis to determine accumulated topography information, wherein accumulated topography information comprises topography information of wafer which includes underlying topography information of the wafer processed by masks of underlying design layers, wherein regions of design layers are categorized according to a topography classification which is based on topographical height in each region relative to a baseline height, and

a second analysis, wherein the second analysis comprises a pattern analysis which comprises matching patterns of the masks to base patterns wherein matching patterns comprises classifying the matched patterns based on the topography profile, wherein the matched pattern is assigned a weight value according to type of topography profile or region; and

generating an enhanced design data file.

14. The process of claim 13 wherein:

the topography analysis comprises performing a simulation using a chemical mechanical polishing (CMP) model to generate topography profile for the IC at different mask levels; and

generating heat maps for different mask levels, wherein the heat map is a color-coded map of the IC based on the topography classification.

15. The process of claim 14 wherein the pattern analysis comprises matching patterns of the mask to base patterns.

16. A process for enhancing a design file for generating a mask set having a plurality of masks used in lithography to form an integrated circuit (IC) on a wafer comprising:

processing a design data file, the design data file comprises information of design layers in an integrated circuit (IC), the information includes patterns of the design layers, wherein processing comprises

performing a topography analysis using a topography analysis module, on the design data file, the topography analysis comprises performing a simulation using a chemical mechanical polishing (CMP) model to generate topography profile for the IC at different design layers or mask levels and regions on the IC of the mask levels are categorized according to a topography classification which is based on topographical height in each region relative to a baseline height; and

performing a pattern analysis on the design data file, the pattern analysis comprises matching patterns of the design layers to base patterns;

generating heat maps for different mask levels, wherein the heat map is a color-coded map of the IC based on the topography classification; and

enhancing using a pattern enhancement module, patterns in the design data file, wherein enhancing comprises

classifying the matched patterns based on the topography profile, wherein the matched pattern is assigned a weight value according to type of topography profile or region, and

fixing the matched patterns based on enhancement priority rule, wherein the enhancement priority rule depends on type of pattern and the weight value; and

generating an enhanced design data file.

17. A system for pattern enhancement of a design data file containing information patterns for an integrated circuit (IC) which is used to generate a mask set having a plurality of masks used to manufacture the IC, the system comprising:

a topography analysis module, the topography analysis module analyzes the design data file containing pattern information of design layers in an IC to determine accumulated topography information of the design layers, wherein regions of design layers are categorized according to a topography classification which is based on topographical height in each region relative to a baseline height;

a pattern analysis module, the pattern analysis module analyzes design layers to identify lithography weak patterns (matched weak lithography patterns) matching known weak lithography patterns wherein the matched weak lithography pattern is assigned a weight value according to type of topography information or region;

a classification module, the classification module classifies matched lithography weak patterns into priority classifications based on the accumulated topography information of the design layer; and

a pattern enhancement module for fixing lithography weak patterns based on their priority classifications.