Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout

• US 9,026,958 B1
• Filed: 03/11/2013
• Issued: 05/05/2015
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ghosh, Sanjib, Parameswaran, Harindranath, Yu, Henry
• Primary Examiner(s): Ngo, Brian
• Application Number:
  US13/794,221
• Time in Patent Office: 785 Days
• Field of Search: 716/50, 716/51, 716/52, 716/54, 716/55, 716/139
• US Class Current: 716/55
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475

Abstract

Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

Claims

1. A computer-implemented method for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout, the method comprising:

mapping, by using a computer, a plurality of violations of the integrated circuit design layout to a graph;

partitioning the graph into a plurality of sub-graphs, wherein each of the plurality of sub-graphs include a plurality of edges and a plurality of nodes, wherein at least one set of the plurality of nodes are collapsible into a single node to enable more accurate inspection of an individual loop;

detecting a plurality of odd loops in each of the plurality of sub-graphs; and

visualizing the plurality of odd loops in both at least one of the plurality of sub-graphs and a corresponding integrated circuit design layout.

2. The computer-implemented method of claim 1, wherein every shape of the integrated circuit layout which is part of a violation is a node of the graph or a sub-graph and every violation between shapes on the integrated circuit layout is an edge of the graph or a sub-graph.

3. The computer-implemented method of claim 1, wherein an odd loop indicates that every shape of the integrated circuit layout which is part of a violation is a node of the graph or a sub-graph.

4. The computer-implemented method of claim 1, wherein every shape of the integrated circuit layout is assigned one of two colors.

5. The computer-implemented method of claim 4, wherein an odd loop indicates a non colorable graph problem between shapes.

6. The computer-implemented method of claim 1, wherein the visualizing step comprises animating the graph in a sub window of a display corresponding to the integrated circuit design layout.

7. The computer-implemented method of claim 1, wherein the visualizing step comprises selecting an edge or node of one of the plurality of sub-graphs and highlighting a corresponding violation on the integrated circuit design layout.

8. The computer-implemented method of claim 1, wherein the visualizing step comprises collapsing multiple nodes into a single node.

9. The computer-implemented method of claim 8, wherein the visualizing step further comprises expanding the single node back to the multiple nodes.

10. The computer-implemented method of claim 1, wherein the odd loops are annotated for the user.

11. The computer-implemented method of claim 1, wherein the violations are sameMaskSpacing violations.

12. A computer program product containing program instructions stored in a non-transitory computer readable storage medium for visualizing derived layer shapes of an integrated circuit design;

the program instruction being executed by a computer;

wherein the computer performs the following steps comprising;

mapping, by using a computer, a plurality of violations of the integrated circuit design layout to a graph;

partitioning the graph into a plurality of sub-graphs, wherein each of the plurality of sub-graphs include a plurality of edges and a plurality of nodes, wherein at least one set of the plurality of nodes are collapsible into a single node to enable more accurate inspection of an individual loop;

detecting a plurality of odd loops in each of the plurality of sub-graphs; and

visualizing the plurality of odd loops in both at least one of the plurality of sub-graphs and a corresponding integrated circuit design layout.

13. The computer program product of claim 12, wherein every shape of the integrated circuit layout which is part of a violation is a node of the graph or a sub-graph and every violation between shapes on the integrated circuit layout is an edge of the graph or a sub-graph.

14. The computer program product of claim 12, wherein an odd loop indicates that every shape of the integrated circuit layout which is part of a violation is a node of the graph or a sub-graph.

15. The computer program product of claim 12, wherein every shape of the integrated circuit layout is assigned one of two colors.

16. The computer program product of claim 15, wherein an odd loop indicates a non colorable graph problem between shapes.

17. The computer program product of claim 12, wherein the visualizing step comprises animating the graph in a sub window of a display corresponding to the integrated circuit design layout.

18. The computer program product of claim 12, wherein the visualizing step comprises selecting an edge or node of one of the plurality of sub-graphs and highlighting a corresponding violation on the integrated circuit design layout.

19. The computer program product of claim 12, wherein the visualizing step further comprises collapsing multiple nodes into a single node.

20. The computer program product of claim 19, wherein the visualizing step comprises expanding the single node back to the multiple nodes.

21. The computer program product of claim 12, wherein the odd loops are annotated for the user.

22. The computer program product of claim 12, wherein the violations are sameMaskSpacing violations.

23. A system for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout, the system comprising:

a graph generator module configured to map a plurality of violations of the integrated circuit design layout to a graph and to partition the graph into a plurality of sub-graphs, wherein each of the plurality of sub-graphs include a plurality of edges and a plurality of nodes, wherein at least one set of the plurality of nodes are collapsible into a single node to enable more accurate inspection of an individual loop;

a detector module for detecting a plurality of possible odd loops in each of the plurality of sub-graphs; and

a visualizer module configured to allow for the visualization of the plurality of odd loops in both at least one of the plurality of sub-graphs and the corresponding integrated circuit design layout.

24. The system of claim 23, wherein every shape of the integrated circuit layout which is part of a violation is a node of the graph or a sub-graph and every violation between shapes on the integrated circuit layout is an edge of the graph or a sub-graph.

25. The system of claim 23, wherein an odd loop indicates that every shape of the integrated circuit layout which is part of a violation is a node of the graph or a sub-graph.

26. The system of claim 23, wherein every shape of the integrated circuit layout is assigned one of two colors.