Method for fabrication of a semiconductor device and structure

• US 9,029,173 B2
• Filed: 10/18/2011
• Issued: 05/12/2015
• Est. Priority Date: 10/18/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Wurman, Ze'ev
• Primary Examiner(s): PARKER, ALLEN L
• Application Number:
  US13/276,312
• Publication Number:
  US 20130095580A1
• Time in Patent Office: 1,302 Days
• Field of Search: 257/118, 257/199, 257/758, 257/E27.074, 438/152, 438/153
• US Class Current: 438/17
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 : Peripheral circuit regions
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/023 : by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/066 : by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.

Claims

1. A method for formation of a semiconductor device, the method comprising:

providing a first mono-crystalline layer comprising first transistors and first alignment marks;

providing an interconnection layer comprising aluminum or copper on top of said first mono-crystalline layer; and

then

forming a second mono-crystalline layer on top of said interconnection layer by using a layer transfer step, and then

processing second transistors on said second mono-crystalline layer comprising a step of forming a gate dielectric,

wherein at least one of said second transistors is a p-type transistor and at least one of said second transistors is an n-type transistor.

2. A method according to claim 1,

wherein said device is part of a low power mobile system.

3. A method according to claim 1, comprising:

replacing a signal generated by said first transistors by a signal generated by said second transistor, or replacing a signal generated by said second transistors by a signal generated by said first transistors.

4. A method according to claim 1, wherein at least one of said second transistors is one of:

(i) a recessed-channel transistor (RCAT);

(ii) a junction-less transistor;

(iii) a replacement-gate transistor;

(iv) a trench MOSFET transistor;

(v) a double gate transistor;

(vi) a Finfet type transistor;

or

(vii) a Dopant Segregated Schottky (DSS-Schottky) transistor.

5. A method according to claim 1, comprising a step of annealing after said layer transfer step.

6. A method according to claim 1,

wherein said second mono-crystalline layer comprises a second alignment mark,

wherein the method further comprises a lithography step comprising an alignment, and

wherein the alignment is based on said first alignment mark and said second alignment mark.

7. A method according to claim 1, comprising a follow on step of etching some of said second transistors.

8. A method according to claim 1, comprising an etch step for the formation of an etch stop indicator,

wherein said etch step is prior to said layer transfer.

9. A method according to claim 1, comprising a step of partitioning a logic design to a first portion to be constructed using said first transistors and a second portion to be constructed by said second transistors,

wherein said step of partitioning includes using manufacturing process nodes as a partition criteria,

wherein a first manufacturing process node utilized to form said first transistors is substantially different that a second manufacturing process node utilized to form said second transistors.

10. A method according to claim 1, comprising implementing a logic design on said device, wherein said step of implementing comprises a synthesis step utilizing at least two libraries, wherein one of said libraries utilizes a substantially different manufacturing process node than the other.

11. A method according to claim 1,

wherein a memory array comprises said second transistors, and

wherein said memory array is a floating body DRAM array.

12. A method according to claim 1,

wherein said layer transfer step utilizes a carrier wafer.

13. A method according to claim 1,

wherein said second transistors are horizontally oriented.