Method of making an insulated gate semiconductor device having a shield electrode structure

• US 9,029,215 B2
• Filed: 05/14/2012
• Issued: 05/12/2015
• Est. Priority Date: 05/14/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hossain, Zia, Grivna, Gordon M., Barber, Duane B., McGrath, Peter, Padmanabhan, Balaji, Venkatraman, Prasad
• Primary Examiner(s): Matthews, Colleen A
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US13/471,105
• Publication Number:
  US 20130302958A1
• Time in Patent Office: 1,093 Days
• Field of Search: 438/270, 438/259, 438/589, 438/591, 438/592, 438/593, 438/595
• US Class Current: 438/259
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Claims

1. A method for making an insulated gate semiconductor device having a shield electrode structure comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a trench extending from the major surface into the region of semiconductor material;

forming a first dielectric layer along surfaces of the trench;

forming a first conductive layer adjacent the first dielectric layer, wherein the first conductive layer is configured as a shield electrode;

removing portions of the first dielectric layer from upper sidewall surfaces of the trench;

thereafter forming a gate dielectric layer along the upper sidewall surfaces of the trench;

forming a first spacer layer adjacent the gate dielectric layer;

forming a second dielectric layer overlying the first conductive layer, wherein the second dielectric layer is formed after the gate dielectric layer is formed;

removing the first spacer layer, wherein the gate dielectric layer remains, at least in part, along the upper sidewall surfaces of the trench after the second dielectric layer is formed and after the first spacer layer is removed; and

forming a second conductive layer adjacent the gate dielectric layer and the second dielectric layer, wherein the second conductive layer is configured as a control electrode.

2. The method of claim 1, wherein the step of forming the first spacer layer comprises forming the first spacer layer comprising an oxidation-resistant material, and wherein the step of removing the first spacer layer comprises etching the first spacer layer.

3. The method of claim 2, wherein the step of forming the first spacer layer comprises forming a nitride spacer layer.

4. The method of claim 1 further comprising the step of forming a second spacer layer between the gate dielectric layer and the first spacer layer.

5. The method of claim 4, wherein the step of forming the second spacer layer comprises forming a crystalline semiconductor spacer layer.

6. The method of claim 1, wherein the step of forming the second dielectric layer comprises forming the second dielectric layer using localized oxidation.

7. The method of claim 1, wherein the step of forming the first conductive layer comprises the step of recessing the first conductive layer below an upper surface of the first dielectric layer.

8. The method of claim 1 further comprising the steps of:

forming a first doped region in the region of semiconductor material, wherein the first doped region and trench are adjacent, and wherein the first doped region has a first conductivity type; and

forming a second doped region adjacent the first doped region, wherein the second doped region has a second conductivity type opposite to the first conductivity type.

9. The method of claim 1 further comprising the steps of

forming a third dielectric layer overlying the major surface;

forming a fourth dielectric layer overlying the third dielectric layer, wherein the third and fourth dielectric layers comprise different materials, and wherein the third and fourth dielectric layers are formed before the step of forming the trench; and

etching to remove the first spacer layer and the fourth dielectric layer after the step of forming the second dielectric layer.

10. The method of claim 1, wherein the step of forming the trench includes forming the trench having sloped sidewalls.

11. The method of claim 1, wherein the step of forming the first dielectric layer comprises the steps of:

forming a first oxide layer comprising a thermal oxide;

forming a second oxide layer comprising a deposited oxide;

removing upper portions of the first and second oxide layers along the upper sidewall surfaces of the trench before the step of forming the gate dielectric layer, wherein the step of removing exposes upper portions of the first conductive layer; and

removing a portion of the first conductive layer to recess the first conductive layer below upper surfaces of the first and second oxide layers.

12. A process for forming an insulated gate semiconductor device comprising the steps of:

forming a first trench in a substrate extending from a major surface;

forming a shield electrode dielectric layer along surfaces of the trench;

forming a shield electrode adjacent the shield electrode dielectric layer, wherein the shield electrode dielectric layer separates the shield electrode from the substrate;

removing portions of the shield electrode dielectric layer from upper sidewall surfaces of the trench;

forming a gate dielectric layer along the upper sidewalls of the trench;

forming a spacer layer along the gate dielectric layer, wherein the spacer layer comprises an oxidation-resistant material;

thereafter forming a dielectric layer overlying the shield electrode using an oxidation process;

removing the spacer layer, wherein the gate dielectric layer remains, at least in part, along the upper sidewall surfaces of the trench after the dielectric layer is formed and after the spacer layer is removed;

forming a gate electrode adjacent the gate dielectric layer;

forming a body region of a first conductivity type in the substrate, wherein the body region and the trench are adjacent; and

forming a source region of a second conductivity type in spaced relationship with the body region.

13. The process of claim 12, wherein the step of forming the spacer layer comprises forming a nitride spacer layer, and wherein the step of removing the spacer layer comprises etching the nitride spacer layer.

14. The process of claim 13 further comprising the step of forming a crystalline semiconductor spacer layer between the nitride spacer layer and the gate dielectric layer.

15. The process of claim 12 further comprising the step of forming a masking layer overlying the major surface before the step of forming the trench, wherein the masking layer includes a dielectric layer, and wherein the dielectric layer and the spacer layer comprise a nitride material.

16. A method for forming a semiconductor device comprising the steps of:

providing a substrate having a trench and a first electrode in a lower portion of the trench and insulated from the substrate by a dielectric layer formed along surfaces of the trench;

removing portions of the dielectric layer along upper sidewall surfaces of the trench;

forming a gate dielectric layer along the upper sidewalls of the trench;

forming a first spacer along the gate dielectric layer;

forming a second spacer layer along the first spacer, wherein the second spacer layer comprises an oxidation-resistant material;

forming an inter-electrode dielectric layer using a localized oxidation process adjacent the first electrode and a lower portion of the gate dielectric layer, wherein the localized oxidation process increases thickness of the lower portion;

removing the second spacer layer; and

forming a second electrode adjacent the first dielectric layer.

17. The method of claim 16, wherein the gate dielectric layer remains, at least in part, along the upper sidewall surfaces of the trench after the inter-electrode dielectric layer is formed and after the second spacer layer is removed.

18. The method of claim 17, wherein the step of forming the second spacer layer comprises forming a nitride spacer layer, and wherein the step of removing the second spacer layer comprises etching the nitride spacer layer.

19. The method of claim 17, wherein the step of forming the first spacer layer comprises forming a polysilicon spacer layer.

20. The method of claim 17, wherein the step of forming the first spacer layer comprising forming an amorphous silicon spacer layer.