Method for manufacturing N-type MOSFET
First Claim
1. A method for manufacturing an N-type MOSFET, comprising:
- forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack;
removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate;
forming an interface oxide layer on the exposed surface of the semiconductor;
forming a high-K gate dielectric layer on the interface oxide layer in the gate opening;
forming a first metal gate layer on the high-K gate dielectric layer;
implanting dopant ions into the first metal gate layer at energy and dosage controlled according to a desired threshold voltage to cause the dopant ions to distribute only in the first metal gate layer, wherein the dopant ions are capable of reducing effective work function;
forming a second metal gate layer on the first metal gate layer to fill the gate opening; and
adjusting an effective work function of the MOSFET by diffusing and thus accumulating, by annealing, the dopant ions at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also generating electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
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Abstract
The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
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Citations
12 Claims
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1. A method for manufacturing an N-type MOSFET, comprising:
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forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer at energy and dosage controlled according to a desired threshold voltage to cause the dopant ions to distribute only in the first metal gate layer, wherein the dopant ions are capable of reducing effective work function; forming a second metal gate layer on the first metal gate layer to fill the gate opening; and adjusting an effective work function of the MOSFET by diffusing and thus accumulating, by annealing, the dopant ions at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also generating electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification