Gallium nitride power devices using island topography
First Claim
1. A semiconductor device comprising:
- a) a substrate;
b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;
c) a metallization layer formed on the nitride semiconductor layer defining an array of a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged with alternating first island electrodes and second island electrodes in at least two orthogonal directions to produce two-dimensional active regions in areas of the nitride semiconductor layer, with;
i) at least one side of each of the first island electrodes opposite a side of the adjacent second island electrodes;
ii) at least one side of each of the second island electrodes opposite a side of adjacent first island electrodes; and
iii) wherein the first island electrodes and second island electrodes serve as source island electrodes and drain island electrodes of a multi-island transistor, or, as anode island electrodes and cathode island electrodes of a multi-island diode;
d) each of the plurality of first island electrodes providing a contact area (pad) for a respective individual first external connection; and
e) each of the plurality of second island electrodes providing a contact area (pad) for a respective individual second external connection; and
f) wherein;
i) said respective individual first and second external connections each comprise a ball, bump or post connection, each first island electrode and each second island electrode having its own individual ball, bump or post connection formed thereon, without on-chip common connections between the first island electrodes and without on-chip common connections between the second island electrodes;
orii) said first external connections each comprise a substrate via connection and said second external connections each comprise a ball, bump or post connection, each second island electrode having its own individual ball, bump or post connection formed thereon, without on-chip common connections between the second island electrodes;
or(iii) said first external connections each comprise a ball, bump or post connection, each first island electrode having its own individual ball, bump or post connection formed thereon, without on-chip common connections between the first island electrodes and said second external connections each comprise a substrate via connection.
1 Assignment
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Accused Products
Abstract
A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes.
129 Citations
22 Claims
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1. A semiconductor device comprising:
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a) a substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a metallization layer formed on the nitride semiconductor layer defining an array of a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other and arranged with alternating first island electrodes and second island electrodes in at least two orthogonal directions to produce two-dimensional active regions in areas of the nitride semiconductor layer, with; i) at least one side of each of the first island electrodes opposite a side of the adjacent second island electrodes; ii) at least one side of each of the second island electrodes opposite a side of adjacent first island electrodes; and iii) wherein the first island electrodes and second island electrodes serve as source island electrodes and drain island electrodes of a multi-island transistor, or, as anode island electrodes and cathode island electrodes of a multi-island diode; d) each of the plurality of first island electrodes providing a contact area (pad) for a respective individual first external connection; and e) each of the plurality of second island electrodes providing a contact area (pad) for a respective individual second external connection; and f) wherein; i) said respective individual first and second external connections each comprise a ball, bump or post connection, each first island electrode and each second island electrode having its own individual ball, bump or post connection formed thereon, without on-chip common connections between the first island electrodes and without on-chip common connections between the second island electrodes; or ii) said first external connections each comprise a substrate via connection and said second external connections each comprise a ball, bump or post connection, each second island electrode having its own individual ball, bump or post connection formed thereon, without on-chip common connections between the second island electrodes; or (iii) said first external connections each comprise a ball, bump or post connection, each first island electrode having its own individual ball, bump or post connection formed thereon, without on-chip common connections between the first island electrodes and said second external connections each comprise a substrate via connection. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification