Semiconductor device

• US 9,029,918 B2
• Filed: 09/14/2011
• Issued: 05/12/2015
• Est. Priority Date: 09/15/2010
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ogura, Tsuneo
• Primary Examiner(s): TORNOW, MARK W
• Application Number:
  US13/232,839
• Publication Number:
  US 20120061724A1
• Time in Patent Office: 1,336 Days
• Field of Search: 257/284
• US Class Current: 257/284
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.

Claims

1. A semiconductor device, comprising:

a first electrode;

a first conductivity-type base layer provided on the first electrode;

a second conductivity-type base layer provided on the first conductivity-type base layer;

a first semiconductor layer of the first conductivity-type provided on the second conductivity-type base layer;

a gate electrode extending from the first semiconductor layer into the second conductivity-type base layer;

a gate insulating film provided between the gate electrode and the first semiconductor layer, between the gate electrode and the second conductivity-type base layer, and between the gate electrode and the first conductivity-type base layer;

a second semiconductor layer of the second conductivity-type selectively provided in the first conductivity-type base layer, the second semiconductor layer contacting the gate insulating film;

a second electrode provided in the second semiconductor layer, the second electrode directly contacting the second semiconductor layer and the gate insulating film; and

a third electrode provided on the first semiconductor layer and being electrically connected to the first semiconductor layer and the second electrode.

2. The device according to claim 1, wherein the gate insulating film is provided between the gate electrode and the second electrode.

3. The device according to claim 1, wherein the second semiconductor layer is directly contacting a bottom face and a side face of the second electrode.

4. The device according to claim 1, wherein the second electrode is a semiconductor containing an impurity and having conductivity.

5. The device according to claim 1, further comprising a third semiconductor layer provided on the first electrode, the third semiconductor layer being a drain layer of the first conductivity type.

6. The device according to claim 1, further comprising a third semiconductor layer provided on the first electrode, the third semiconductor layer beinq a collector layer of the second conductivity type.

7. The device according to claim 1, wherein the first semiconductor layer is provided in a striped planar pattern overlapped on the second conductivity-type base layer with a same width as the second conductivity-type base layer.