Field effect transistor devices with low source resistance

• US 9,029,945 B2
• Filed: 05/06/2011
• Issued: 05/12/2015
• Est. Priority Date: 05/06/2011
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Ryu, Sei-Hyung, Capell, Doyle Craig, Cheng, Lin, Dhar, Sarit, Jonas, Charlotte, Agarwal, Anant, Palmour, John
• Primary Examiner(s): Jung, Michael
• Application Number:
  US13/102,510
• Publication Number:
  US 20120280252A1
• Time in Patent Office: 1,467 Days
• Field of Search: None
• US Class Current: 257/341
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Claims

1. A semiconductor device, comprising:

a drift layer having a first conductivity type;

a well region in the drift layer having a second conductivity type opposite the first conductivity type;

a source region in the well region, the source region having the first conductivity type and defining a channel region in the well region, wherein the source region comprises a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region;

a body contact region having the second conductivity type between at least two of the plurality of source contact regions and in contact with the well region; and

a source ohmic contact that is on at least one of the source contact regions and the body contact region, and that is not on the lateral source region, wherein the source ohmic contact is on the at least one of the source contact regions in a source contact region area and the source ohmic contact is on the body contact region in a body contact region area, and wherein a ratio of a minimum dimension p1 of the body contact region area to a minimum dimension w1 of the well region on a same plane as the body contact region area is greater than 0.2, wherein the body contact region comprises a plurality of body contact regions that are interspersed between the source contact regions and contact the source ohmic contact, and wherein ones of the plurality of body contact regions are not physically contacting other ones of the plurality of body contact regions.

2. The semiconductor device of claim 1, wherein the plurality of body contact regions are spaced apart from the channel region by the lateral source region.

3. The semiconductor device of claim 1, wherein a ratio of a minimum dimension n1 of the source contact region area to a minimum dimension w1 of the well region is greater than 0.2.

4. The semiconductor device of claim 3, wherein the ratio of the minimum dimension n1 of the source contact region area to the minimum dimension w1 of the well region is between 0.3 and 1.

5. The semiconductor device of claim 3, wherein the ratio of the minimum dimension n1 of the source contact region area to the minimum dimension w1 of the well region is greater than 0.5.

6. The semiconductor device of claim 1, wherein the ratio of the minimum dimension p1 of the body contact region area to the minimum dimension w1 of the well region is greater than about 0.3.

7. The semiconductor device of claim 1, wherein the ratio of the minimum dimension p1 of the body contact region area to the minimum dimension w1 of the well region is greater than about 0.5.

8. The semiconductor device of claim 1, wherein the drift region comprises a wide bandgap semiconductor material having a baudgap greater than 2.0 V.

9. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide.

10. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide having at least one of a 2H, 4H and 6H polytype.

11. The semiconductor device of claim 8, wherein the drift region comprises silicon carbide having at least one of a 3C and 15R polytype.

12. The semiconductor device of claim 1, wherein the source region has a sheet resistance and the source ohmic contact has a contact resistance, wherein the plurality of source contact regions are arranged in a layout such that a ratio of the sheet resistance in ohms per square to the contact resistance in ohms per square area is greater than 1, wherein the square is equal in size to the square area.

13. The semiconductor device of claim 1, wherein the device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 700 amps per square centimeter.

14. The semiconductor device of claim 1, wherein the semiconductor device comprises a field effect transistor.

15. The semiconductor device of claim 1, wherein the semiconductor device comprises an insulated gate bipolar transistor.

16. The semiconductor device of claim 1, wherein each of the plurality of body contact regions is laterally adjacent to the lateral source region.

17. The semiconductor device of claim 16, further comprising a second lateral source region adjacent to ends of the plurality of body contact regions opposite the lateral source region, wherein the second lateral source region separates the plurality of body contact regions from a second channel.

18. The semiconductor device of claim 1, wherein each of the plurality of body contact regions is in contact with the source ohmic contact.

19. A semiconductor device, comprising:

a drift layer having a first conductivity type;

a well region having a second conductivity type that is opposite the first conductivity type;

a source region in the well region, the source region having the first conductivity type;

a body contact region having the second conductivity type in contact with the well region; and

a source ohmic contact that is on the source region in a source contact region area and that is on the body contact region in a body contact region area;

wherein a ratio of a smallest width dimension n1 of the source contact region area to a smallest width dimension w1 of the well region on a same plane as the source contact region area is greater than 0.3, wherein the body contact region is between both ends of the smallest width dimension w1.

20. The semiconductor device of claim 19, wherein the ratio of the smallest width dimension n1 of the source contact region area to the smallest width dimension w1 of the well region is greater than 0.5.

21. A semiconductor device, comprising:

a drift layer having a first conductivity type;

a well region having a second conductivity type that is opposite the first conductivity type;

a source region in the well region, the source region having the first conductivity type;

a body contact region having the second conductivity type in contact with the well region; and

a source ohmic contact that is on the source region in a source contact area and that is on the body contact region in a body contact region area;

wherein a ratio of a smallest width dimension p1 of the body contact region area to a smallest width dimension w1 of the well region on a same plane as the body contact region area is greater than 0.2, wherein the body contact region is between both ends of the smallest width dimension w1.

22. The semiconductor device of claim 21, wherein the ratio of the smallest width dimension p1 of the body contact region area to the smallest width dimension w1 of the well region is greater than about 0.3.

23. The semiconductor device of claim 21, wherein the ratio of the smallest width dimension p1 of the body contact region area to the smallest width dimension w1 of the well region is greater than about 0.5.