Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
First Claim
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1. A semiconductor device comprising:
- an epitaxy layer formed on a semiconductor substrate;
a device layer formed on the epitaxy layer;
an opening formed within the semiconductor substrate and including a dielectric layer forming a liner and a conductive core within the opening forming a signal through-silicon via, wherein the signal through-silicon via extends through the device layer and the epitaxy layer; and
an isolating through-silicon via formed within the substrate and surrounding the signal through-silicon via, wherein the isolating through-silicon via extends through the device layer and the epitaxy layer, such that the isolating through-silicon via forms a ring around the signal through-silicon via, wherein a region of the epitaxy layer formed inside the ring between the isolating through-silicon via and the signal through-silicon via is electrically isolated from another region of the epitaxy layer that is formed outside the ring when a voltage is applied to the signal through-silicon via.
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Abstract
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
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Citations
5 Claims
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1. A semiconductor device comprising:
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an epitaxy layer formed on a semiconductor substrate; a device layer formed on the epitaxy layer; an opening formed within the semiconductor substrate and including a dielectric layer forming a liner and a conductive core within the opening forming a signal through-silicon via, wherein the signal through-silicon via extends through the device layer and the epitaxy layer; and an isolating through-silicon via formed within the substrate and surrounding the signal through-silicon via, wherein the isolating through-silicon via extends through the device layer and the epitaxy layer, such that the isolating through-silicon via forms a ring around the signal through-silicon via, wherein a region of the epitaxy layer formed inside the ring between the isolating through-silicon via and the signal through-silicon via is electrically isolated from another region of the epitaxy layer that is formed outside the ring when a voltage is applied to the signal through-silicon via. - View Dependent Claims (2, 3, 4, 5)
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Specification