Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance

• US 9,029,988 B2
• Filed: 01/17/2013
• Issued: 05/12/2015
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Iyer, Subramanian S., Kerber, Pranita, Khakifirooz, Ali
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US13/743,882
• Publication Number:
  US 20130127067A1
• Time in Patent Office: 845 Days
• Field of Search: 257/621, 257/698, 257/276, 257/E23.067
• US Class Current: 257/621
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

Claims

1. A semiconductor device comprising:

an epitaxy layer formed on a semiconductor substrate;

a device layer formed on the epitaxy layer;

an opening formed within the semiconductor substrate and including a dielectric layer forming a liner and a conductive core within the opening forming a signal through-silicon via, wherein the signal through-silicon via extends through the device layer and the epitaxy layer; and

an isolating through-silicon via formed within the substrate and surrounding the signal through-silicon via, wherein the isolating through-silicon via extends through the device layer and the epitaxy layer, such that the isolating through-silicon via forms a ring around the signal through-silicon via, wherein a region of the epitaxy layer formed inside the ring between the isolating through-silicon via and the signal through-silicon via is electrically isolated from another region of the epitaxy layer that is formed outside the ring when a voltage is applied to the signal through-silicon via.

2. The semiconductor device of claim 1, wherein the signal through-silicon via is of a larger depth in the substrate and larger width than a depth and a width of the isolating through-silicon via.

3. The semiconductor device of claim 1, wherein the region of the epitaxy layer is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers.

4. The semiconductor device of claim 1, wherein the epitaxy layer is an n+ epitaxy layer.

5. The semiconductor device of claim 4, wherein the epitaxy layer has a doping level above approximately of about 1×

10¹⁹ atoms/cm³ or greater.