Chip package with die and substrate

• US 9,030,029 B2
• Filed: 01/22/2002
• Issued: 05/12/2015
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US10/055,568
• Publication Number:
  US 20030122246A1
• Time in Patent Office: 4,858 Days
• Field of Search: 257/777, 257/778, 257/700, 257/516, 257/758, 257/782, 438/106, 438/107, 438/612, 438/121
• US Class Current: 257/782
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Claims

1. A chip package comprising:

a substrate having a first surface at a first height and a second surface at a second height, said first height different from said second height, said substrate having opposing sidewalls between said first surface and said second surface of said substrate, in which said opposing sidewalls and said first surface of said substrate define an opening in said substrate;

only one singulated die positioned in said opening in said substrate, said singulated die having a first surface opposite said first surface of said substrate and a second surface opposite said first surface of said singulated die;

an adhesive material joining said first surface of said substrate and said second surface of said only one die, wherein said adhesive material comprises an adhesive tape joining said first surface of said substrate and said second surface of said only one die;

a first insulating layer coupled to said only one die, coupled to said substrate and across an edge of said only one die, wherein said first insulating layer comprises a first portion vertically over said only one die and a second portion not vertically over said only one die, wherein said first insulating layer is not integrated with said adhesive material;

a patterned circuit layer over said first insulating layer, said first horizontal level, said only one die and said substrate and across said edge, wherein said patterned circuit layer is connected to said only one die through a first opening in said first insulating layer;

a passive device over said first horizontal level and said first insulating layer, wherein said passive device comprises an inductor; and

a second insulating layer over said passive device.

2. The chip package of claim 1, wherein said only one die comprises a first trace formed therein, and wherein said patterned circuit layer comprises a second trace having a thickness greater than that of said first trace.

3. The chip package of claim 1, wherein said patterned circuit layer comprises a power bus.

4. The chip package of claim 1, wherein said patterned circuit layer comprises a ground bus.

5. The chip package of claim 1, wherein said patterned circuit layer connects multiple portions of said only one die.

6. The chip package of claim 1, wherein said first insulating layer comprises polyimide.

7. The chip package of claim 1, wherein said first insulating layer comprises benzocyclobutene (BCB).

8. The chip package of claim 1, wherein said adhesive material comprises a conductive paste joining said top surface of said substrate and said bottom surface of said only one die.

9. The chip package of claim 1, wherein said patterned circuit layer comprises an electroplated metal.

10. The chip package of claim 1, wherein said patterned circuit layer comprises a sputtered metal.

11. The chip package of claim 1, wherein said passive device has a portion vertically over said substrate but not vertically over said only one die.

12. The chip package of claim 1 further comprising a metal bump having a portion vertically over said substrate but not vertically over said only one die.

13. The chip package of claim 1 further comprising a polymer layer on said substrate, wherein said only one die is between a first portion of said polymer layer and a second portion of said polymer layer.

14. The chip package of claim 13, wherein said polymer layer comprises epoxy.

15. The chip package of claim 1 further comprising a solder interconnect coupled to a first level.

16. The chip package of claim 1 further comprising a gold interconnect coupled to a first level.

17. The chip package of claim 1, wherein said only one die comprises multiple active devices, and said patterned circuit layer connects said multiple active devices.

18. The chip package of claim 1, wherein said substrate comprises a silicon substrate.

19. The chip package of claim 1, wherein said patterned circuit layer comprises copper.

20. The chip package of claim 1, wherein said substrate comprises a metal layer.

21. The chip package of claim 1, wherein said passive device comprises copper.