Circuit structure of test-key and test method thereof

• US 9,030,221 B2
• Filed: 09/20/2011
• Issued: 05/12/2015
• Est. Priority Date: 09/20/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tso, Ching-Yu
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): LE, THANG XUAN
• Application Number:
  US13/236,737
• Publication Number:
  US 20130069682A1
• Time in Patent Office: 1,330 Days
• Field of Search: 324/760.01, 324/760.02, 32476201-76203, 324/762.08, 324/762.09, 714/1, 716/4, 702/108, 345/904
• US Class Current: 324/755.01
• CPC Class Codes: G01R 31/27 Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements testing printed circuit boards G01R31/2801
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: Y10S 345/904 Display with fail/safe testing feature

Abstract

A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on.

Claims

1. A test method of a test-key, the circuit structure of the test-key comprising a plurality of transistors, a first conductive contact pad, a plurality of second conductive contact pads and a plurality of third conductive contact pads, the transistors being arranged in a matrix, the first conductive contact pad being electrically coupled to a first source/drain terminal of each of the transistors in each column of the matrix, each of the second conductive contact pads being electrically coupled to a second source/drain terminal of each of the transistors in a corresponding column of the matrix, and each of the third conductive contact pads being electrically coupled to a gate terminal of each of the transistors in a corresponding row of the matrix, the test method comprising:

providing a plurality of driving pulses to the third conductive contact pads respectively according to a predetermined sequence, so as to turn on the transistors row-by-row, wherein the enabling periods of two adjacent driving pulses in time do not overlap;

providing a test signal to the first conductive contact pad during a test; and

reading out a plurality of output signals as test results from the second conductive contact pads when a row of the transistors is turned on, so as to perform an element-character analyzing operation accordingly.

2. The test method of the test-key according to claim 1, wherein the circuit structure of the test-key further comprises a plurality of passive components, each of the passive components has two terminals, and each of the passive components is electrically coupled to the first source/drain terminal of a corresponding one of the transistors and the first conductive contact pad or between the second source/drain terminal of a corresponding one of the transistors and a corresponding one of the second conductive contact pads.

3. The test method of the test-key according to claim 2, wherein the passive components comprises at least one resistor.

4. The test method of the test-key according to claim 2, wherein the passive components comprises at least one capacitor.

5. The test method of the test-key according to claim 1, wherein each of the transistors is a metal-oxide transistor field-effect transistor.

6. The test method of the test-key according to claim 1, wherein the driving pulses are generated by a scan-pulse generating circuit, the scan-pulse generating circuit is electrically coupled to the third conductive contact pads, so as to provide the driving pulses to the third conductive contact pads respectively according to the predetermined sequence.

7. The test method of the test-key according to claim 6, wherein the scan-pulse generating circuit comprises:

a clock generator configured, for generating a clock signal; and

a plurality of shift registers, the shift registers being connected in series, an output terminal of each of the shift registers being electrically coupled to a corresponding one of the third conductive contact pads, each of the shift registers receiving the clock signal for outputting a driving pulse, so as to use the driving pulse to turn on the transistors in a corresponding row corresponding to a third conductive contact pad which receives the driving pulse, and the enabling periods of two driving pulses outputted from two adjacent shift registers do not overlap.