Level shifter with output spike reduction
First Claim
1. A level shifter apparatus having at least one level-shifted final output ranging from about a positive supply rail voltage VDD in a first state to about a negative supply rail voltage VSS in a second state, either of the two states adapted to be selected based on value of an input control signal operating within a range substantially different from the range between the negative supply rail voltage VSS and the positive supply rail voltage VDD, the level shifter comprising:
- a) a first inverting circuit and a second inverting circuit configured to output a first inverter output voltage and a second inverter output voltage, respectively, to a first final output circuit, the first final output circuit configured to produce a level-shifted final output based on the first inverter output voltage and the second inverter output voltage, wherein;
i) the first inverter output voltage is within a range from about a common voltage to about the positive supply rail voltage VDD,ii) the second inverter output voltage is within a range from about the common voltage to about the negative supply rail voltage VSS, andiii) in either of the first and second states of the level-shifted final output, one of the inverter output voltages is either at about the negative supply rail voltage VSS or at about the positive supply rail voltage VDD and the other inverter output voltage is at about the common voltage; and
b) a first transition control circuitry and a second transition control circuitry connected with the first inverting circuit and the second inverting circuit, respectively, each of the transition control circuitries configured to delay a transition of a corresponding inverter output voltage from around the common voltage toward either about the negative supply rail voltage VSS or about the positive supply rail voltage VDD until the other inverter output voltage has significantly transitioned from either about the negative supply rail voltage VSS or about the positive supply rail voltage VDD toward the common voltage.
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Accused Products
Abstract
A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.
153 Citations
21 Claims
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1. A level shifter apparatus having at least one level-shifted final output ranging from about a positive supply rail voltage VDD in a first state to about a negative supply rail voltage VSS in a second state, either of the two states adapted to be selected based on value of an input control signal operating within a range substantially different from the range between the negative supply rail voltage VSS and the positive supply rail voltage VDD, the level shifter comprising:
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a) a first inverting circuit and a second inverting circuit configured to output a first inverter output voltage and a second inverter output voltage, respectively, to a first final output circuit, the first final output circuit configured to produce a level-shifted final output based on the first inverter output voltage and the second inverter output voltage, wherein; i) the first inverter output voltage is within a range from about a common voltage to about the positive supply rail voltage VDD, ii) the second inverter output voltage is within a range from about the common voltage to about the negative supply rail voltage VSS, and iii) in either of the first and second states of the level-shifted final output, one of the inverter output voltages is either at about the negative supply rail voltage VSS or at about the positive supply rail voltage VDD and the other inverter output voltage is at about the common voltage; and b) a first transition control circuitry and a second transition control circuitry connected with the first inverting circuit and the second inverting circuit, respectively, each of the transition control circuitries configured to delay a transition of a corresponding inverter output voltage from around the common voltage toward either about the negative supply rail voltage VSS or about the positive supply rail voltage VDD until the other inverter output voltage has significantly transitioned from either about the negative supply rail voltage VSS or about the positive supply rail voltage VDD toward the common voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of developing, in a level shifter circuit, at least one output signal that substantially approaches an upper supply rail voltage VDD in a first state and substantially approaches a lower supply rail voltage VSS in a second state, either of the two states adapted to be selected based on value of an input control signal to the level shifter that falls suitably within an input control signal range that is substantially smaller than the range from the upper supply rail voltage VDD to the lower supply rail voltage VSS, the method comprising the steps of:
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a) applying the input control signal to a first inverting block to generate a first inverter output voltage and applying the input control signal to a second inverting block to generate a second inverter output voltage, wherein; i) the first inverter output voltage is within a range from about a common voltage to about the upper supply rail voltage VDD, ii) the second inverter output voltage is within a range from about the common voltage to about the lower supply rail voltage VSS, and iii) in either of the first and second states of the at least one output signal, one of the inverter output voltages is either at about the lower supply rail voltage VSS or at about the upper supply rail voltage VDD and the other inverter output voltage is at about the common voltage; b) applying the first and second inverter output voltages to a first output block to generate a first output signal among the at least one output signal; and c) during each transition of the at least one output signal between the first and second states initiated by a change in the input control signal, delaying initiation of a transition by the inverter output voltage that is at about the common voltage until after the other inverter output voltage that is either at about the upper supply rail voltage VDD or about the lower supply rail voltage VSS has significantly transitioned toward the common voltage. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification