Display apparatus

• US 9,030,460 B2
• Filed: 07/09/2012
• Issued: 05/12/2015
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Woongkwon, Kim, Sungryul, Kim, Daecheol, Mun, Sungjin, Park, Kyung-ho, Bang, Jung suk, Jeong, Ki-Hun, Cho, Byeonghoon, Han, Kun-Wook, Kim, Jaewon
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): Khoo, Stacy
• Application Number:
  US13/544,690
• Publication Number:
  US 20130229401A1
• Time in Patent Office: 1,037 Days
• Field of Search: 345 87-100, 345/103, 345204-213, 345/101, 349/49, 349/149, 349/150, 349/152
• US Class Current: 345/212
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2360/14 Detecting light within display terminals, e.g. using a single or a plurality of photosensors
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A display apparatus includes pixels, a driver for providing a driving voltage, and conductive lines including a first line, a second line, and a third line. The display apparatus further includes a first circuit electrically connected to the driver for receiving the driving voltage and electrically connected to the pixels for controlling the pixels. The first circuit includes a first chip, a first inner line, a first pad, a second pad, a third pad, a fourth pad, and a fifth pad. The first chip is electrically connected to the driver through the third pad, the fourth pad, the fifth pad, the third line, the second line, the second pad, the first inner line, the first pad, and the first line. The fourth and fifth pads may contribute to consistent resistance for paths that transmit the driving voltage, for enabling desirable display quality of the display apparatus.

Claims

1. A display apparatus comprising:

a first plurality of pixels disposed at a first portion of a display area;

a second plurality of pixels disposed at a second portion of the display area;

a third plurality of pixels disposed at a third portion of the display area;

a driver for providing a driving voltage;

a plurality of electrically conductive lines including a first line, a second line, a third line, a fourth line, a fifth line, a sixth line;

a first circuit electrically connected to the driver for receiving the driving voltage and electrically connected to the first plurality of pixels for controlling the first plurality of pixels, the first circuit including a first chip, a first inner line, a first pad of the first circuit, a second pad of the first circuit, a third pad of the first circuit, a fourth pad of the first circuit, a fifth pad of the first circuit, wherein the first chip is electrically connected to the driver through the third pad of the first circuit, the fourth pad of the first circuit, the fifth pad of the first circuit, the third line, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line;

a second circuit electrically connected to the driver for receiving the driving voltage and electrically connected to the second plurality of pixels for controlling the second plurality of pixels, the second circuit including a second chip, a second inner line, a first pad of the second circuit, a second pad of the second circuit, a third pad of the second circuit, wherein the second chip is electrically connected to the driver through the third pad of the second circuit, the fifth line, the fourth line, the second pad of the second circuit, the second inner line, the first pad of the second circuit, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line; and

a third circuit electrically connected to the driver for receiving the driving voltage and electrically connected to the third plurality of pixels for controlling the third plurality of pixels, the third circuit including a third chip and a first pad of the third circuit, wherein the third chip is electrically connected to the driver through the first pad of the third circuit, the sixth line, the fourth line, the second pad of the second circuit, the second inner line, the first pad of the second circuit, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line,

wherein resistance of the third line is substantially equal to a sum of resistance of the second inner line, resistance of the fourth line, and resistance of the fifth line.

2. The display apparatus of claim 1, wherein the first chip is sequentially and electrically connected through the third pad of the first circuit, the fourth pad of the first circuit, the fifth pad of the first circuit, the third line, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line to the driver.

3. The display apparatus of claim 1, wherein the second chip is sequentially and electrically connected through the third pad of the second circuit, the fifth line, the fourth line, the second pad of the second circuit, the second inner line, the first pad of the second circuit, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line to the driver.

4. The display apparatus of claim 1, wherein contact resistance associated with the first pad of the second circuit is substantially equal to contact resistance associated with the fourth pad of the first circuit.

5. The display apparatus of claim 1, wherein the third chip is sequentially and electrically connected through the first pad of the third circuit, the sixth line, the fourth line, the second pad of the second circuit, the second inner line, the first pad of the second circuit, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line to the driver.

6. The display apparatus of claim 1, wherein contact resistance associated with the first pad of the third circuit is substantially equal to contact resistance associated with the third pad of the second circuit.

7. The display apparatus of claim 1, wherein resistance of the sixth line is substantially equal to resistance of the fifth line.

8. The display apparatus of claim 1, wherein each of the fifth line and the sixth line is electrically connected to the fourth line at a node, and wherein the fifth line is mechanically connected to the sixth line at the node.

9. The display apparatus of claim 8, wherein the node is positioned such that resistance of the fifth line is substantially equal to resistance of the sixth line.

10. The display apparatus of claim 1, wherein a first edge of the first circuit is disposed closer to the driver than a second edge of the first circuit and is disposed farther from the third pad of the first circuit then the second edge of the first circuit, the third pad of the first circuit being electrically connected between the first chip and the first pad of first circuit, and wherein a first edge of the third circuit is disposed closer to the driver than a second edge of the third circuit and is disposed closer to the first pad of the third circuit than the second edge of the third circuit, the first pad of the third circuit not being electrically connected between the third chip and any other pads of the third circuit.

11. The display apparatus of claim 1, wherein the first circuit further includes a sixth pad of the first circuit and a seventh pad of the first circuit, and wherein the first chip is electrically connected through the third pad of the first circuit, the fourth pad of the first circuit, the fifth pad of the first circuit, the sixth pad of the first circuit, and the seventh pad of the first circuit to the third line.

12. The display apparatus of claim 1, wherein the second circuit further includes a fourth pad of the second circuit and a fifth pad of the second circuit, wherein the second chip is electrically connected to the driver through the third pad of the second circuit, the fourth pad of the second circuit, the fifth pad of the second circuit, the fifth line, the fourth line, the second pad of the second circuit, the second inner line, the first pad of the second circuit, the second line, the second pad of the first circuit, the first inner line, the first pad of the first circuit, and the first line.

13. The display apparatus of claim 1, further comprising a data line for transmitting a data signal, wherein the first plurality of pixels includes a first pixel that includes a transistor, and wherein the first circuit is configured to provide a gate-on voltage to the transistor for enabling the pixel to receive the data signal.

14. The display apparatus of claim 1, further comprising a read-out line for transmitting a predetermined voltage, wherein the first plurality of pixels includes a first pixel associated with a light sensor that includes a transistor and a capacitor, and wherein the first circuit is configured to provide a scan signal to the transistor for enabling the capacitor to receive the predetermined voltage.