Stable fast programming scheme for displays

• US 9,030,506 B2
• Filed: 12/18/2013
• Issued: 05/12/2015
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Nathan, Arokia
• Primary Examiner(s): Lao, Lun-Yi
• Assistant Examiner(s): McLoone, Peter D
• Application Number:
  US14/132,840
• Publication Number:
  US 20140104325A1
• Time in Patent Office: 510 Days
• Field of Search: 345/76, 345/77, 345/82, 345/211, 345/690
• US Class Current: 345/690
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A technique for improving the spatial and/or temporal uniformity of a light-emitting display by providing a faster calibration of reference current sources and reducing the noise effect by improving the dynamic range, despite instability and non-uniformity of the transistor devices. A calibration circuit for a display panel having an active area having a plurality of light emitting devices arranged on a substrate, and a peripheral area of the display panel separate from the active area is provided. The calibration circuit includes a first row of calibration current source or sink circuits and a second row of calibration current source or sink circuits. A first calibration control line is configured to cause the first row of calibration current source or sink circuits to calibrate the display panel with a bias current while the second row of calibration current source or sink circuits is being calibrated by a reference current. A second calibration control line is configured to cause the second row of calibration current source or sink circuits to calibrate the display panel with the bias current while the first row of calibration current source or sink circuits is being calibrated by the reference current.

Claims

1. A display panel, comprising:

a plurality of pixel circuits arranged in columns and rows relative to a substrate, each of the pixel circuits including a light emitting device that is turned on or off by a drive transistor;

a controller;

a controllable current source or sink circuit controlled by the controller that controls a supply of a bias current to at least one of the columns of the pixel circuits in the display panel; and

a current source or sink address driver controlled by the controller that activates selected one or ones of the columns of the pixel circuits to receive the bias current;

wherein the controllable current source or sink circuit includes an arrangement of transistors and a first capacitor such that a voltage across the first capacitor is determined by device parameters of a first of the transistors, whereby the bias current supplied by the controllable current source or sink circuit is stable and compensated for variations in the device parameters.

2. The display panel of claim 1, wherein the transistors include the first transistor, a second transistor, and a third transistor, where the first, second, and third transistors and the first capacitor are connected to a common node, the first transistor being connected to provide a discharge path for the first capacitor to discharge through the third transistor to develop the voltage across the first capacitor that is determined by the device parameters of the first transistor in response to a controllable bias voltage being applied to the second transistor.

3. The display panel of claim 2, wherein the first transistor is in a diode-connected configuration while providing the conduction path for the first capacitor to discharge through the third transistor.

4. The display panel of claim 2, wherein the second transistor is turned on to apply the controllable bias voltage to charge the capacitor to the controllable bias voltage, followed by turning on the third transistor to cause the first capacitor to discharge through the third transistor.

5. The display panel of claim 2, wherein the transistors include a fourth transistor, a fifth transistor, and a sixth transistor, where the capacitor includes a second capacitor, the fourth, fifth, and sixth transistors and the second capacitor are connected to a second common node, the fourth transistor being connected to provide a discharge path for the second capacitor to discharge through the sixth transistor such that a voltage across the second capacitor is determined by device parameters of the fourth transistor.

6. The display panel of claim 5, the controllable current source or sink circuit having a high output impedance to allow higher immunity to output voltage fluctuations.

7. The display panel of claim 1, wherein the arrangement of the transistors and the first capacitor forms at least two compensation circuit blocks where a current developed by one of the at least two compensation circuit blocks adjusts another current developed by another of the at least two compensation circuit blocks.

8. A method of supplying a stable bias current to a column of pixel circuits in a display panel by a current source or sink circuit, comprising:

staggering at least two compensation circuit blocks of the current source or sink circuit to achieve multiple compensations of device parameters by;

developing in the current source or sink circuit a first voltage determined by device parameters associated with a first transistor of the current source or sink circuit;

developing in the current source or sink circuit a second voltage determined by device parameters associated with a second transistor connected to the first transistor such that the second transistor adjusts a current flowing through the first transistor; and

supplying to the column of pixel circuits a stable bias current that is multiply compensated for variations in the device parameters associated with the first and second transistors.

9. The method of claim 8, further comprising charging a first capacitor in the current source or sink circuit to a first bias voltage and discharging the voltage across the first capacitor so that a final voltage across the first capacitor is influenced by the device parameters associated with the first transistor.

10. The method of claim 9, further comprising charging a second capacitor in the current source or sink circuit to a second bias voltage and discharging the voltage across the second capacitor so that a final voltage across the second capacitor is influenced by device parameters associated with the second transistor.

11. The method of claim 8, further comprising selectively activating transistors of the current source or sink circuit to first develop the first bias voltage across the first capacitor and then to discharge the voltage across the first capacitor to the final voltage.

12. The method of claim 8, wherein the supplying is carried out in response to the second transistor'"'"'s adjusting the current flowing through the first transistor.

13. The method of claim 8, further comprising applying a first bias voltage to the current source or sink circuit and operating the first transistor in a diode-connected configuration to cause the first voltage to be developed.

14. The method of claim 13, further comprising applying a second bias voltage to the current source or sink circuit and operating the second transistor in a diode-connected configuration to cause the second voltage to be developed.