In-plane switching mode liquid crystal display and method for fabricating the same
First Claim
1. A method for fabricating an in-plane switching (IPS) type liquid crystal display (LCD) device, comprising:
- forming gate lines arranged in a first direction and data lines arranged in a second direction substantially perpendicular to the first direction, the gate lines and the data lines defining pixel regions on an array substrate;
forming a storage electrode on the array substrate;
forming common electrodes extending across each pixel region;
forming pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region;
forming thin film transistors (TFTs) at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode; and
forming a common line under one of the common electrodes in the pixel region, the common line being substantially parallel to the data lines,wherein the common line is underneath the respective common electrode to overlap the common electrode, andwherein the common line and the data lines are formed on a first insulating layer on the array substrate with the gate electrode, the gate line and the storage electrode formed thereon.
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Abstract
A method for fabricating an in-plane switching (IPS) type liquid crystal display (LCD) device according to an embodiment includes forming gate lines arranged in a first direction and data lines arranged in a second direction substantially perpendicular to the first direction, the gate lines and the data lines defining pixel regions on an array substrate; forming a storage electrode on the array substrate; forming common electrodes extending across each pixel region; forming pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region; and forming thin film transistors (TFTs) at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode.
12 Citations
14 Claims
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1. A method for fabricating an in-plane switching (IPS) type liquid crystal display (LCD) device, comprising:
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forming gate lines arranged in a first direction and data lines arranged in a second direction substantially perpendicular to the first direction, the gate lines and the data lines defining pixel regions on an array substrate; forming a storage electrode on the array substrate; forming common electrodes extending across each pixel region; forming pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region; forming thin film transistors (TFTs) at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode; and forming a common line under one of the common electrodes in the pixel region, the common line being substantially parallel to the data lines, wherein the common line is underneath the respective common electrode to overlap the common electrode, and wherein the common line and the data lines are formed on a first insulating layer on the array substrate with the gate electrode, the gate line and the storage electrode formed thereon. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for fabricating an in-plane switching (IPS) mode liquid crystal display (LCD) device, comprising:
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forming a gate electrode and a gate line on a first substrate; forming a first insulating layer on the first substrate; forming an active pattern on the first substrate; forming source and drain electrodes on the first substrate and forming an data line crossing the gate line to define a pixel area; forming a storage electrode on the first substrate; forming at least one common line in a direction substantially parallel to the data line within the pixel area of the first substrate; forming a second insulating layer on the first substrate; and forming a plurality of common electrodes and pixel electrodes alternately disposed within the pixel area of the first substrate to generate an in-plane field, such that at least one common electrode is positioned over an upper portion of the common line, wherein the common line is underneath the respective common electrode to overlap the common electrode, and wherein the common line and the data lines are formed on the first insulating layer on the first substrate with the gate electrode, the gate line and the storage electrode formed thereon. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification