Bipolar CMOS select device for resistive sense memory

• US 9,030,867 B2
• Filed: 07/13/2009
• Issued: 05/12/2015
• Est. Priority Date: 10/20/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Lu, Yong, Liu, Hongyue, Khoury, Maroun, Chen, Yiran
• Primary Examiner(s): Nguyen, Vanthu
• Assistant Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US12/502,211
• Publication Number:
  US 20100177554A1
• Time in Patent Office: 2,129 Days
• Field of Search: 365/177, 365/179, 365/148, 365/158
• US Class Current: 365/177
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode

Abstract

A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

Claims

1. A resistive sense memory apparatus comprising:

a bipolar select device comprising;

a semiconductor substrate;

a plurality of field effect transistors disposed in the semiconductor substrate and forming a row of field effect transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other, a gate contact layer extends along a channel region between the emitter contact and a collector contact;

a base contact layer is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact layer and the base contact layer, the base contact layer extends along a length of the row of field effect transistors and provides a body bias to each field effect transistor in the row of field effect transistors at the same time; and

a plurality of resistive sense memory cells, wherein one of the plurality of resistive sense memory cells is electrically between one of the collector contacts or emitter contacts and a bit line.

2. A resistive sense memory apparatus according to claim 1, wherein the collector contacts and the emitter contacts have N type conductivity and the base layer has P+ type conductivity.

3. A resistive sense memory apparatus according to claim 2, wherein each field effect transistor further comprises a layer of P−

type conductivity separating the base layer from the collector contacts and the emitter contacts.

4. A resistive sense memory apparatus according to claim 1, wherein the collector contacts and the emitter contacts have P type conductivity and the base layer has N+ type conductivity.

5. A resistive sense memory apparatus according to claim 4, wherein each field effect transistor further comprises a layer of N−

type conductivity separating the base layer from the collector contacts and the emitter contacts.

6. A resistive sense memory apparatus according to claim 1, wherein the resistive sense memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

7. A resistive sense memory apparatus according to claim 1, wherein the gate contact layer is a common gate contact layer for the row of field effect transistors and extends along a length of the row of field effect transistors and the common gate contact layer is co-extensive with the base contact layer along a length of the row of field effect transistors.

8. A resistive sense memory apparatus according to claim 1, further comprising a plurality of bipolar select devices, wherein each bipolar select device forms a row of a memory array.

9. A resistive sense memory apparatus according to claim 8, wherein each bipolar select device is electrically isolated from each other.

10. A resistive sense memory array, comprising:

a plurality of bipolar select devices, each bipolar select device forming a row of a memory array, each bipolar select device comprising;

a semiconductor substrate;

a plurality of field effect transistors disposed in the semiconductor substrate and forming a row of field effect transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other, a gate contact layer extends along a channel region between the emitter contact and a collector contact, the gate contact layer is a common gate contact layer for the row of field effect transistors and extends along a length of the row of field effect transistors;

a base contact layer is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact layer and the base contact layer, the base contact layer extends along a length of the row of field effect transistors and provides a body bias to each field effect transistor in the row of field effect transistors at the same time, and the gate contact layer is co-extensive with the base contact layer along a length of the row of field effect transistors; and

a plurality of resistive sense memory cells, wherein one of the plurality of resistive sense memory cells is electrically between one of the collector contacts or emitter contacts and a bit line.

11. A resistive sense memory array according to claim 10, wherein each bipolar select device is electrically isolated from each other.

12. A resistive sense memory array according to claim 10, wherein the resistive sense memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

13. A resistive sense memory array according to claim 10, further comprising a plurality of bipolar select devices, wherein each bipolar select device forms a row of a memory array.

14. A resistive sense memory array according to claim 10, wherein the collector contacts and the emitter contacts have N type conductivity and the base layer has P+ type conductivity and each field effect transistor further comprises a layer of P−

type conductivity separating the base layer from the collector contacts and the emitter contacts.

15. A resistive sense memory array according to claim 10, wherein the collector contacts and the emitter contacts have P type conductivity and the base layer has N+ type conductivity and each field effect transistor further comprises a layer of N−

type conductivity separating the base layer from the collector contacts and the emitter contacts.

16. A method, comprising:

writing a first data state to a plurality of resistive sense memory cells by applying a forward bias across a bipolar CMOS select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to, wherein the bipolar CMOS select device comprises;

a semiconductor substrate;

a plurality of field effect transistors disposed in the semiconductor substrate and forming a row or transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other, a gate contact layer extends along a channel region between the emitter contact and a collector contact;

a base contact layer is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact layer and the base contact layer, the base contact layer extends along a length of the row of field effect transistors and provides a body bias to each field effect transistor in the row of field effect transistors at the same time.

17. A method according to claim 16, further comprising writing a second data state to a plurality of resistive sense memory cells by applying a reverse bias across bipolar CMOS select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to.

18. A method according to claim 16, wherein the gate contact layer is a common gate contact layer for the row of transistors and extends along a length of the row of transistors and the gate contact layer is co-extensive with the base contact layer along a length of the row of transistors.