Method of maintaining the state of semiconductor memory having electrically floating body transistor

• US 9,030,872 B2
• Filed: 07/31/2014
• Issued: 05/12/2015
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/448,757
• Publication Number:
  US 20140340972A1
• Time in Patent Office: 285 Days
• Field of Search: 365/185.05, 365/185.18
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. An integrated circuit comprising:

an array of memory cells formed in a semiconductor having at least one surface, the array comprising;

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each said memory cell comprising;

a floating body region;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region;

wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels; and

a control circuit configured to provide electrical signals to at least one of said back bias region and said first or second regions.

2. The integrated circuit of claim 1, wherein said electrical signals have an amplitude or polarity dependent on an operation of said array of memory cells.

3. The integrated circuit of claim 1, wherein said control circuit is configured to provide electrical signals to one of said first or second regions.

4. The integrated circuit of claim 1, wherein said control circuit is configured to provide electrical signals to said back bias region.

5. The integrated circuit of claim 1, wherein said control circuit comprises a first control circuit configured to provide electrical signals to one of said first or second regions, said integrated circuit further comprising a second control circuit configured to provide electrical signals to said back bias region.

6. The integrated circuit of claim 4 wherein said control circuit comprises a voltage generator circuit.

7. The integrated circuit of claim 6, further comprising a multiplexer electrically connected between said voltage generator circuit and said back bias region, said multiplexer configured to apply periodic pulses of positive voltage to said back bias region.

8. The integrated circuit of claim 1, wherein said control circuit comprises a reference generator circuit configured to sense potential of said floating body region.

9. The integrated circuit of claim 1, wherein said control circuit comprises a read circuit connected to one of said first or second region and configured to read a state of said memory cell.

10. The integrated circuit of claim 9, further comprising a reference generator circuit connected to said read circuit.

11. An integrated circuit comprising:

an array of memory cells formed in a semiconductor having at least one surface, the array comprising;

a plurality of said memory cells arranged in a plurality of rows and a plurality of columns, each said memory cell comprising;

a floating body region;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back bias region, wherein said back-bias region is commonly connected to at least two of said memory cells and configured to inject charge into or extract charge out of said floating body region of each of said memory cells connected thereto, to maintain states of said at least two of said memory cells in parallel; and

a control circuit configured to provide electrical signals to at least one of said back bias region and said first or second regions.

12. The integrated circuit of claim 11, wherein said electrical signals have an amplitude or polarity dependent on an operation of said array of memory cells.

13. The integrated circuit of claim 11, wherein said control circuit is configured to provide electrical signals to one of said first or second regions.

14. The integrated circuit of claim 11, wherein said control circuit is configured to provide electrical signals to said back bias region.

15. The integrated circuit of claim 11, wherein said control circuit comprises a first control circuit configured to provide electrical signals to one of said first or second regions, said integrated circuit further comprising a second control circuit configured to provide electrical signals to said back bias region.

16. The integrated circuit of claim 14, wherein said control circuit comprises a voltage generator circuit.

17. The integrated circuit of claim 16, further comprising a multiplexer electrically connected between said voltage generator circuit and said back bias region, said multiplexer configured to apply periodic pulses of positive voltage to said back bias region.

18. The integrated circuit of claim 11, wherein said control circuit comprises a reference generator circuit configured to sense potential of said floating body region.

19. The integrated circuit of claim 11, wherein said control circuit comprises a read circuit connected to one of said first or second region and configured to read a state of said memory cell.

20. The integrated circuit of claim 19, further comprising a reference generator circuit connected to said read circuit.