Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

• US 9,030,877 B2
• Filed: 10/11/2012
• Issued: 05/12/2015
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Strenz, Robert, Langheinrich, Wolfram, Roehrich, Mayk, Wiesner, Robert
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/649,978
• Publication Number:
  US 20130033934A1
• Time in Patent Office: 943 Days
• Field of Search: 365/185.14, 365/185.18, 365/185.27, 365/185.28, 365/185.29
• US Class Current: 365/185.14
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Claims

1. A memory cell arrangement, comprising:

a substrate;

at least one memory cell, comprising a charge storing memory cell structure, a select structure, a first source/drain region located proximate to the select structure and a second source/drain region located distant from the select structure, wherein the select structure comprises a select gate configured as a spacer and laterally disposed from a sidewall of the charge storing memory cell structure;

a first doping well and a second doping well, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well and the second doping well is arranged within the substrate;

a bitline coupled to the first source/drain region located proximate to the select structure; and

a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed and erased by charging and discharging the charge storing memory cell structure via at least the first doping well,

wherein the control circuit is configured to program the charge storing memory cell structure by source side injection comprising applying electrical voltages to the select structure, the charge storing memory cell structure, the first source/drain region through the bitline and second source/drain region, such that electrons in a channel region located between the first and second source/drain regions are accelerated from the first source/drain region located proximate to the select structure towards the second source/drain region located distant from the select structure and are injected into the charge storing memory cell structure from a part of the channel region located under the charge storing memory cell structure and proximate to the select structure, and

wherein the control circuit is configured to erase the charge storing memory cell structure by Fowler-Nordheim erase via at least the first doping well.

2. The memory cell arrangement of claim 1, wherein the control circuit is configured to apply, during programming of the charge storing memory cell structure, first and second electrical voltages, respectively, to the first and second source/drain regions, the second electrical voltage being higher than the first electrical voltage, and third and fourth electrical voltages, respectively, to the select structure and the charge storing memory cell structure, the third and fourth electrical voltages being positive and the fourth electrical voltage being higher than the third electrical voltage.

3. The memory cell arrangement of claim 2, wherein the charge storing memory cell structure is a floating gate memory cell structure.

4. The memory cell arrangement of claim 1, further comprising:

a first wordline structure coupled with the memory cell and the control circuit; and

a second wordline structure coupled with another memory cell comprising another charge storing memory cell structure,

wherein the control circuit is configured to provide a wordline inhibit voltage to the second wordline and thereby to the other charge storing memory cell structure when erasing the charge storing memory cell structure.

5. The memory cell arrangement of claim 4, wherein the wordline inhibit voltage is substantially equal to a voltage provided to at least one of the first and second doping wells.

6. The memory cell arrangement of claim 4, wherein the wordline inhibit voltage is lower than a voltage provided to at least one of the first and second doping wells.

7. The memory cell arrangement of claim 1, further comprising at least one additional doping well arranged within the substrate, wherein the second doping well is arranged within the at least one additional doping well.

17. The memory array of claim 1, wherein the control circuit is configured to connect the substrate to a ground voltage and to apply a first voltage to the first doping well and the second doping well during an erase process, wherein the first voltage is greater than the ground voltage.

8. A memory array, comprising:

a plurality of memory cells, each memory cell comprising a charge storing memory cell structure, a select structure, a first source/drain region arranged proximate to the select structure and a second source/drain region located distant from the select structure of the memory cell, and first and second doping wells arranged within a substrate, the charge storing memory cell structure being arranged in or above the first doping well, the first doping well being arranged within the second doping well, and the second doping well being arranged within the substrate, the select structure comprising a select gate configured as a spacer and laterally disposed from a sidewall of the charge storing memory cell structure;

a plurality of bitlines, each bitline being coupled to at least two of the first source/drain regions arranged proximate to the select structures of the memory cells; and

control circuitry coupled with the plurality of memory cells and configured to control the memory cells such that the charge storing memory cell structure of each memory cell is programmed or erased by charging or discharging the charge storing memory cell structure of the respective memory cell via at least the first doping well,

wherein the control circuitry is configured to control the memory cells such that the charge storing memory cell structure of each memory cell is programmed by applying electrical voltages to the select structure, the charge storing memory cell structure and the first and second source/drain regions of the respective memory cell, such that electrons in a channel region located between the first and second source/drain regions are accelerated from the first source/drain region located proximate to the select structure towards the second source/drain region located distant from the select structure and are injected into the charge storing memory cell structure from a part of the channel region located under the charge storing memory cell structure and proximate to the select structure.

9. The memory array of claim 8, wherein the control circuitry is configured to apply, during programming of the charge storing memory cell structure of a memory cell, first and second electrical voltages, respectively, to the first and second source/drain regions of the memory cell, the second electrical voltage being higher than the first electrical voltage, and third and fourth electrical voltages, respectively, to the select structure and the charge storing memory cell structure of the memory cell, the third and fourth electrical voltages being positive and the fourth electrical voltage being higher than the third electrical voltage.

10. The memory array of claim 8,

wherein the memory cells are arranged in rows and columns,

wherein a bitline in each case is provided for a column of memory cells, and

wherein for all memory cells in a column, the first source/drain region arranged proximate to the select structure of the respective memory cell is coupled to the bitline provided for that column.

11. The memory array of claim 10, wherein a control line in each case is provided for a row of memory cells, and wherein for all memory cells in a row, the second source/drain region arranged distant from the select structure of the respective memory cell is coupled to the control line provided for that row.

18. The memory array of claim 8, wherein the control circuit is configured to erase the charge storing memory cell structure by Fowler-Nordheim erase via at least the first doping well, wherein the control circuit is configured to connect the substrate to a ground voltage and to apply a first voltage to the first doping well and the second doping well during an erase process, wherein the first voltage is greater than the ground voltage.

12. A memory array, comprising:

a plurality of memory cells, each memory cell comprising a charge storing memory cell structure, a select structure, a first source/drain region arranged proximate to the select structure and a second source/drain region located distant from the select structure of the memory cell, and first and second doping wells arranged within a substrate, the charge storing memory cell structure being arranged in or above the first doping well, the first doping well being arranged within the second doping well, and the second doping well being arranged within the substrate, the select structure comprising a select gate configured as a spacer and laterally disposed from a sidewall of the charge storing memory cell structure;

a plurality of bitlines, each bitline being coupled to at least two of the first source/drain regions arranged proximate to the select structures of the memory cells; and

control circuitry coupled with the plurality of memory cells and configured to control the memory cells such that the charge storing memory cell structure of each memory cell is programmed or erased by charging or discharging the charge storing memory cell structure of the respective memory cell via at least the first doping well,

wherein the control circuitry is configured to control the memory cells such that the charge storing memory cell structure of each memory cell is programmed by applying first and second electrical voltages, respectively, to the first and second source/drain regions of the respective memory cell, the second electrical voltage being higher than the first electrical voltage, and applying third and fourth electrical voltages, respectively, to the select structure and the charge storing memory cell structure of the respective memory cell, the third and fourth electrical voltages being positive and the fourth electrical voltage being higher than the third electrical voltage.

13. The memory array of claim 12,

wherein the memory cells are arranged in rows and columns,

wherein a bitline in each case is provided for a column of memory cells, and

wherein for all memory cells in a column, the first source/drain region arranged proximate to the select structure of the respective memory cell is coupled to the bitline provided for that column.

14. The memory array of claim 13,

wherein a control line in each case is provided for a row of memory cells, and

wherein for all memory cells in a row, the second source/drain region arranged distant from the select structure of the respective memory cell is coupled to the control line provided for that row.

15. The memory array of claim 12, wherein the control circuitry comprises an erase circuit that is configured to erase the charge storing memory cell structure of each memory cell by Fowler-Nordheim erase via at least the first doping well of the respective memory cell.

16. The memory array of claim 15, wherein the erase circuit is configured to connect the substrate to a ground voltage and to apply a first voltage to the first doping well and the second doping well during an erase process, wherein the first voltage is greater than the ground voltage.