Memory device and driving method thereof

• US 9,030,886 B2
• Filed: 12/07/2012
• Issued: 05/12/2015
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Hsin-Wen
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/707,601
• Publication Number:
  US 20140160840A1
• Time in Patent Office: 886 Days
• Field of Search: 365/189.011, 365/189.11, 365/210.12, 365/185.24
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A memory device includes a memory array, an array gap, a voltage provider, and a voltage divider. The voltage provider is disposed in the array gap and coupled to a column of memory cells of the memory array for providing a first voltage to the column of memory cells when a memory cell of the column is selected at a write cycle. The voltage provider is coupled to the voltage provider and the column of memory cells for providing a second voltage lower than the first voltage to the column of memory cells when the memory of the column is half selected at the write cycle.

Claims

1. A memory device comprising:

a memory array comprising;

a plurality of columns of memory cells, each memory cell of the columns of memory cells comprising a plurality of PMOS (P-type metal oxide semiconductor) switches;

an array gap;

a voltage provider disposed in the array gap coupled to N-wells of PMOS switches of each memory cell of a column of memory cells of the plurality of columns of memory cells for providing a first voltage to the N-wells when a logic level of a bit line coupled to the column of memory cells and a logic level of a bit line bar coupled to the column of memory cells are inverse to one another; and

a voltage divider coupled to the voltage provider and the N-wells for dividing the first voltage to provide a second voltage lower than the first voltage to the N-wells when the logic level of the bit line and the logic level of the bit line bar are substantially the same.

2. The memory device of claim 1 wherein the voltage divider is disposed in the array gap.

3. The memory device of claim 1 wherein each memory cell of the column of memory cells is a non-volatile memory cell.

4. The memory device of claim 1 wherein each memory cell of the column of memory cells is an SRAM cell.

5. A memory device comprising:

a memory array comprising;

a plurality of columns of memory cells, each memory cell of the columns of memory cells comprising a plurality of NMOS (N-type metal oxide semiconductor) switches;

an array gap;

a first voltage provider disposed in the array gap coupled to P-wells of NMOS switches of each memory cell of a column of memory cells of the plurality of columns of memory cells for providing a first voltage to the P-wells when a logic level of a bit line coupled to the column of memory cells and a logic level of a bit line bar coupled to the column of memory cells are inverse to one another; and

a second voltage provider coupled to the P-wells for providing a second voltage lower than the first voltage to the P-wells when the logic level of the bit line and the logic level of the bit line bar are substantially the same.

6. The memory device of claim 5 wherein the second voltage provider is disposed in the array gap.

7. The memory device of claim 5 wherein each memory cell of the column of memory cells is a non-volatile memory cell.

8. The memory device of claim 5 wherein each memory cell of the column of memory cells is an SRAM cell.

9. A memory device comprising:

a memory array comprising;

a plurality of columns of memory cells, each memory cell of the columns of memory cells comprising a plurality of PMOS (P-type metal oxide semiconductor) switches;

an array gap;

a voltage provider disposed in the array gap coupled to sources of PMOS switches of each memory cell of a column of memory cells of the plurality of columns of memory cells for providing a first voltage to the sources when a logic level of a bit line coupled to the column of memory cells and a logic level of a bit line bar coupled to the column of memory cells are substantially the same; and

a voltage divider coupled to the voltage provider and the sources for dividing the first voltage to provide a second voltage lower than the first voltage to the sources when the logic level of the bit line and the logic level of the bit line bar are inverse to one another.

10. The memory device of claim 9 wherein the voltage divider is disposed in the array gap.