Memory device with post package repair, operation method of the same and memory system including the same

• US 9,030,899 B2
• Filed: 12/15/2013
• Issued: 05/12/2015
• Est. Priority Date: 10/07/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Joo-Hyeon
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/106,832
• Publication Number:
  US 20150098287A1
• Time in Patent Office: 513 Days
• Field of Search: 365/200
• US Class Current: 365/200
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

An operation method of a memory device includes entering a repair mode, changing an input path of setting data from a set path to a repair path in response to the entering of the repair mode, receiving the setting data together with a setting command, ending the repair mode after the receiving is repeated a set number of times, changing the input path of the setting data from the repair path to the set path in response to the ending of the repair mode, and programming a repair address for a defective memory cell of the memory device to a nonvolatile memory using the setting data.

Claims

1. An operation method of a memory device, comprising:

entering a repair mode;

changing an input path of setting data from a set path to a repair path in response to the entering of the repair mode;

receiving the setting data together with a setting command;

ending the repair mode after the receiving is repeated a set number of times;

changing the input path of the setting data from the repair path to the set path in response to the ending of the repair mode; and

programming a repair address for a defective memory cell of the memory device to a nonvolatile memory using the setting data,

wherein, in the receiving of the setting data together with the setting command, the setting command is transmitted at a rising edge of a clock and the setting data is transmitted at a falling edge of the clock.

2. The operation method of claim 1, wherein, in a memory array of the memory device, memory cells corresponding to the repair address programmed to the nonvolatile memory are replaced with redundancy memory cells.

3. The operation method of claim 1, wherein the memory device includes a LPDDR (Low Power Double Data Rate) memory device.

4. A memory device comprising:

a command input unit suitable for receiving one or more command signals;

a command/address input unit suitable for receiving a plurality of command/address signals;

a command decoder suitable for decoding the command signals and the command/address signals, to determine whether to enter a repair mode and generate a setting command;

a setting circuit suitable for setting the memory device using signals inputted through the command/address input unit in response to the setting command in other modes than the repair mode; and

a nonvolatile memory circuit suitable for programming a repair address for a defective memory cell of the memory device using the signals inputted through the command/address input unit in response to the setting command in the repair mode,

wherein the nonvolatile memory circuit comprises;

a nonvolatile memory;

a plurality of pipe latches suitable for storing setting data of the signals inputted through the command/address input unit;

an address/data classification section suitable for classifying the setting data stored in the plurality of pipe latches into an address and data and

a control section suitable for controlling the data classified by the address/data classification section to be programmed to a position designated by the address classified by the address/data classification section in the nonvolatile memory.

5. The memory device of claim 4, further comprising:

a memory array including a plurality of memory cells;

a register suitable for receiving and storing the repair address stored in the nonvolatile memory circuit in an initial operation of the memory device; and

a repair circuit suitable for replacing memory cells corresponding to the repair address stored in the register in the memory array with redundancy memory cells.

6. The memory device of claim 4, wherein the command decoder activates a repair mode signal at an entry of the repair mode by determining whether to enter the repair mode through the decoding.

7. The memory device of claim 6, further comprising:

a path selection unit suitable for transferring the signals inputed through the command/address input unit to the setting circuit or the nonvolatile memory circuit in response to the repair mode signal.

8. The memory device of claim 6, wherein the command decoder deactivates the repair mode signal when the setting command is activated a set number of times after the entry of the repair mode.

9. The memory device of claim 4, wherein the memory device includes a LPDDR (Low Power Double Data Rate) memory device.

10. An operation method of a memory system, comprising:

determining whether a memory device enters a repair mode in response to one or more command signals and command/address signals inputted from a memory controller;

changing an input path of the one or more command signals and the command/address signals in the memory device based on the determining for the memory device of entering the repair mode;

applying the one or more command signals and the command/address signals from the memory controller to the memory device a set number of times in the repair mode; and

programming a repair address for a defective memory cell of the memory device to a nonvolatile memory of the memory device using the command/address signals,

wherein, in the applying of the one or more command signals and the command/address signals, the one or more command signals are transmitted at a rising edge of clock and the command/address signals are transmitted at a falling edge of the clock.

11. The operation method of claim 10, further comprising:

ending the repair mode of the memory device after the applying of the one or more command signals and the command/address signals; and

changing the input path of the one or more command signals and the command/address signals in the memory device after the ending of the repair mode.