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Method, apparatus and instructions for parallel data conversions

  • US 9,032,003 B2
  • Filed: 09/24/2012
  • Issued: 05/12/2015
  • Est. Priority Date: 09/08/2003
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a register file including a first packed data register and a second packed data register;

    a decoder to decode a first instruction;

    scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution; and

    execution logic coupled to the decoder and the scheduling logic;

    wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed signed data elements to a plurality of unsigned results, whereinthe plurality of first packed signed data elements from the first packed data register is converted to the plurality of unsigned results,the unsigned results are saturated and stored in the second packed data register, andeach of the first packed signed data elements has a first number of bits, each of the unsigned results has a second number of bits, and the second number of bits is one half the first number of bits; and

    wherein the processor is to be coupled to;

    a memory,a communication interface to send and receive data via a network, anda graphics interface to store image data.

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