Transaction re-ordering

• US 9,032,103 B2
• Filed: 12/06/2012
• Issued: 05/12/2015
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David J., Rosenbluth, Mark B., Bhatt, Ajay V., Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert G., Falik, Ohad, Mendelson, Avi, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): MARTINEZ, DAVID E
• Application Number:
  US13/706,575
• Publication Number:
  US 20130097353A1
• Time in Patent Office: 887 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

an I/O element to;

receive a plurality of transactions over a PCIe-compliant interconnect, wherein the plurality of transactions are to be received in a first order and include a subset of transactions each referencing a particular memory location;

identify a relaxed ordering value included in at least one of the plurality of transactions; and

reorder the plurality of transactions into a second, different order based at least in part on the relaxed ordering value, wherein a particular one of the plurality of transactions is to precede another of the plurality of transactions in the first order and is to follow the other transaction in the second order and priority of transactions within the subset of transactions is to be maintained in the second order.

2. The apparatus of claim 1, wherein at least one of the particular transaction and other transaction includes an atomic operation.

3. The apparatus of claim 1, wherein the plurality of transactions is to be completed according to the second order.

4. The apparatus of claim 1, wherein the I/O element is included in a root controller of the apparatus.

5. The apparatus of claim 1, wherein the plurality of transactions is to be reordered on the interconnect.

6. The apparatus of claim 1, wherein the subset of transactions comprises a first transaction and a second transaction, the first transaction has priority over the second transaction in the first order, and ordering rules require that priority of the first transaction over the second transaction in the first order be maintained in the second order.

7. The apparatus of claim 6, wherein the first transaction comprises a read request of a particular memory location and the second transaction comprises a write request of the particular memory location.

8. The apparatus of claim 1, wherein the plurality of transactions are to be completed according to the second order.

9. The apparatus of claim 8, wherein the plurality of transactions include one or more of a memory write request, a memory read request, a message request, an I/O read request, and an I/O write request.

10. The apparatus of claim 1, wherein the relaxed ordering value comprises a value of a relaxed ordering header field of at least one packet included in the plurality of transactions.

11. The apparatus of claim 10, wherein the relaxed ordering header field comprises a single bit.

12. An apparatus comprising:

an I/O element to;

generate a packet to be included in a plurality of transactions to include a relaxed ordering value to indicate that relaxed ordering applies to at least a particular one of the plurality of transactions, wherein the plurality of transactions are to include a subset of transactions each referencing a particular memory location;

send the packet over a PCIe-compliant interconnect, wherein the plurality of transactions are to be sent in a first order and the relaxed ordering value allows the plurality of transactions to be completed according to a second, different order, wherein priority of transactions is the subset of transactions, as defined in the first order, is to be maintained in the second order.

13. The apparatus of claim 12, wherein the packet is a packet of the particular transaction and the particular transaction is to precede another of the plurality of transactions in the first order and is to follow the other transaction in the second order.

14. The apparatus of claim 13, wherein the reordering causes the subset of transactions to be ordered according to a sequential addressing of memory targeted by the subset of transactions.

15. The apparatus of claim 13, wherein the reordering causes a reduction in service time for completing the subset of transactions.

16. The apparatus of claim 13, wherein the reordering mitigates congestion on the interconnect.

17. The apparatus of claim 12, wherein the reordering improves efficiency of completion of at least a subset of the plurality of transactions.

18. The apparatus of claim 12, wherein the relaxed ordering value is a value of a relaxed ordering field included in a header of the packet.

19. An apparatus comprising:

a root controller configured to;

receive a plurality of transactions over a point-to-point PCIe-compliant interconnect, wherein the root controller includes an I/O module including a protocol stack including a transaction layer, a link layer, and a physical layer, and the plurality of transactions include transaction layer packets each including a transaction layer header, and wherein the plurality of transactions are to be received in a first order, a particular one of the plurality of transactions follows another one of the plurality of transactions in the first order, and the plurality of transactions includes a subset of transactions each referencing a particular memory location;

identify that relaxed ordering applies to the particular transaction based at least in part on a value of an ordering attribute field of the particular transaction, wherein the ordering attribute field comprises a single bit; and

reorder at least the particular transaction in the plurality of transactions, wherein the plurality of transactions are in a different second order following the reordering, the particular transaction precedes the other transaction in the second order, the reordering allows the particular transaction to be completed prior to the other transaction, and priority of transactions is the subset of transactions, as defined in the first order, is to be maintained in the second order.

20. The apparatus of claim 19, wherein relaxed ordering is to allow at least one of:

a) a received write request of the particular transaction to pass a received write request in the other transaction; and

b) a received read request of the particular transaction to pass a received write request in the other transaction.

21. A method comprising:

receiving a plurality of transactions over a PCIe-compliant interconnect, wherein the plurality of transactions are received in a first order;

identifying a relaxed ordering value included in at least one of the plurality of transactions;

identifying that a subset of the plurality of transactions each reference a particular memory location; and

reordering the plurality of transactions into a second, different order based at least in part on the relaxed ordering value, wherein the plurality of transactions are in a second order following the reordering and priority of the subset of transactions in the first order is maintained in the second order.

22. The method of claim 21, further comprising causing the plurality of transactions to be completed according to the second order.

23. The method of claim 21, wherein the relaxed ordering value is included in at least a particular one of the plurality of transactions, the method further comprising identifying that relaxed ordering applies to the particular transaction, wherein the second order is based at least in part on the reordering of the particular transaction.

24. The method of claim 23, wherein the relaxed ordering value is included in at least one packet header of the particular transaction.

25. A system comprising:

a first device;

a second device, including an I/O module executed by at least one processor to;

receive a plurality of transactions over a PCIe-compliant interconnect, wherein the plurality of transactions are received in a first order and at least one of the transactions is requested by the first device;

identify a relaxed ordering value included in at least one of the plurality of transactions;

identify that a subset of the plurality of transactions each reference a particular memory location;

reorder the plurality of transactions into a second, different order based at least in part on the relaxed ordering value, wherein the plurality of transactions are in a second order following the reordering and priority of the subset of transactions in the first order is maintained in the second order; and

cause the plurality of transactions to be completed according to the second order.

26. The system of claim 25, wherein the first computing device is communicatively coupled to the second computing device using the interconnect.

27. The system of claim 25, wherein the first device comprises a root controller hub.