Memory systems and block copy methods thereof

• US 9,032,272 B2
• Filed: 11/30/2012
• Issued: 05/12/2015
• Est. Priority Date: 12/06/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Sangyong, Park, Kitae, Han, Jinman
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US13/690,544
• Publication Number:
  US 20130145234A1
• Time in Patent Office: 893 Days
• Field of Search: 714/773, 365/185.18, 711/103
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using, for example, an address-scrambled reprogramming technique.

Claims

1. A method of operating a nonvolatile memory device, comprising:

performing error checking and correction (ECC) operations on M pages of data read from a first portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two; and

programming a second portion of M-bit nonvolatile memory cells within the nonvolatile memory device with the M pages of ECC-processed data using an address-scrambled reprogramming technique.

2. The method of claim 1, wherein the nonvolatile memory device comprises multiple nonvolatile memory chips;

and wherein the first and second portions of M-bit nonvolatile memory cells are located on the same or separate nonvolatile memory chips within the nonvolatile memory device.

3. The method of claim 1, wherein said address-scrambled reprogramming technique comprises programming a plurality of M-bit nonvolatile memory cells at least M−

1 times.

4. The method of claim 1, wherein said address-scrambled reprogramming technique comprises programming a plurality of M-bit nonvolatile memory cells into a respective plurality of program states and then reprogramming the plurality of M-bit nonvolatile memory cells so that threshold voltages of the plurality of M-bit nonvolatile memory cells are changed but their respective plurality of program states remain unchanged.

5. The method of claim 4, wherein the address-scrambled reprogramming technique comprises programming a target page of M-bit nonvolatile memory cells M times using a 2^M-1-2^M-2^M programming sequence or a 2^M-2^M-2^M programming sequence.

6. The method of claim 1, wherein said performing ECC operations is preceded by reading M-pages of data from a source page of M-bit nonvolatile memory cells into a page buffer associated with a first block of nonvolatile memory within the nonvolatile memory device.

7. The method of claim 6, wherein said performing ECC operations is preceded by sequentially transferring the M-pages of data from the page buffer to an ECC circuit.

8. The method of claim 7, wherein the nonvolatile memory device comprises at least one nonvolatile memory chip;

and wherein the page buffer and ECC circuit are located on the same nonvolatile memory chip.

9. The method of claim 7, wherein the nonvolatile memory device comprises a nonvolatile buffer memory of single-bit nonvolatile memory cells;

and wherein said programming is preceded by transferring the M pages of ECC-processed data to the nonvolatile buffer memory.

10. The method of claim 9, wherein said programming is preceded by reading the M pages of ECC-processed data from the nonvolatile buffer memory into the page buffer.

11. The method of claim 9, wherein said programming comprises reading the M pages of ECC-processed data from the nonvolatile buffer memory into the page buffer multiple times.

12. The method of claim 9, wherein said programming is performed concurrently with reading the M pages of ECC-processed data from the nonvolatile buffer memory into the page buffer.

13. The method of claim 7, wherein the ECC circuit is located within a memory controller comprising a random access buffer memory;

and wherein said programming is preceded by transferring the M pages of ECC-processed data to the random access buffer memory and then to the page buffer.

14. The method of claim 7, wherein the ECC circuit is located within a memory controller comprising a random access buffer memory;

and wherein said programming is preceded by transferring the M pages of ECC-processed data directly from the ECC circuit to the page buffer.

15. The method of claim 1, wherein the address-scrambled reprogramming technique comprises programming the second portion of M-bit nonvolatile memory cells associated with a first word line at least first and second times;

and wherein the address-scrambled reprogramming technique comprises programming a third portion of M-bit nonvolatile memory cells associated with a second word line between the first and second times.