Semiconductor device with a low-k spacer and method of forming the same

• US 9,034,701 B2
• Filed: 01/20/2012
• Issued: 05/19/2015
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B, Khakifirooz, Ali, La Tulipe, Douglas C
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Parker, John M
• Application Number:
  US13/354,363
• Publication Number:
  US 20130187229A1
• Time in Patent Office: 1,215 Days
• Field of Search: 438/183, 438/300
• US Class Current: 438/183
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.

Claims

1. A method of forming a device, comprising:

providing a semiconductor substrate;

forming a dummy gate stack on the semiconductor substrate;

forming dummy spacers adjacent to the dummy gate stack;

forming raised source/drain (RSD) regions on the semiconductor substrate adjacent to the dummy spacers;

forming an ILD layer on the dummy spacers and the RSD regions;

removing the dummy gate stack and the dummy spacers;

forming low-k spacers adjacent to the RSD regions, wherein the low-k spacers are embedded in the ILD layer; and

forming a replacement gate stack on the semiconductor substrate, the replacement gate stack including a gate dielectric layer on the semiconductor substrate and a gate conductor layer on the gate dielectric layer.

2. The method according to claim 1, wherein the semiconductor substrate comprises a semiconductor-on-insulator (SOI) substrate having an ETSOI layer, a BOX layer and a substrate layer.

3. The method according to claim 2, wherein the ETSOI layer has a thickness in a range from about 3 nm to about 10 nm.

4. The method according to claim 1, wherein the gate dielectric layer comprises a high-k material.

5. The method according to claim 4, wherein the high-k material is selected from the group consisting of:

hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

6. The method according to claim 1, wherein the gate conductor layer comprises a metal.

7. The method according to claim 6, wherein the metal is selected from the group consisting of:

tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver and gold.

8. The method according to claim 1, further comprising forming thin nitride spacers between the gate dielectric layer, the low-k spacers and the ILD layer.

9. The method according to claim 8, wherein the thin nitride spacers have a width in a range from about 2 nm to about 6 nm.