Method of forming a micro device transfer head with silicon electrode

• US 9,034,754 B2
• Filed: 05/25/2012
• Issued: 05/19/2015
• Est. Priority Date: 05/25/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Golda, Dariusz, Bibl, Andreas
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US13/481,615
• Publication Number:
  US 20130316529A1
• Time in Patent Office: 1,089 Days
• Field of Search: None
• US Class Current: 438/637
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0284 Details of three-dimensional rigid printed circuit boards H05K1/119 takes precedence; shaping of the substrate H05K3/0014
• CPC Class Codes: H05K 1/03 Use of materials for the substrate
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate

Abstract

A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect. A dielectric layer covers a top surface of each mesa structure.

Claims

1. A method of forming a micro device transfer head array comprising:

etching a top silicon layer of a silicon-on-insulator stack to form a silicon interconnect and a plurality of silicon electrodes electrically connected with the silicon interconnect, each silicon electrode including a mesa structure that protrudes above the silicon interconnect; and

forming a dielectric layer over the plurality of silicon electrodes.

2. The method of claim 1, further comprising forming a mask layer on the top silicon layer, and patterning the mask layer to form a plurality of islands.

3. The method of claim 2, wherein forming the mask layer comprises thermally oxidizing the top silicon layer.

4. The method of claim 2, further comprising:

using the plurality of islands as an etching mask, etching a plurality of trenches partially through the top silicon layer; and

removing the plurality of islands from the top silicon layer; and

etching the top silicon layer to form the silicon interconnect and the plurality of silicon electrodes.

5. The method of claim 4, wherein etching the top silicon layer to form the silicon interconnect and the plurality of silicon electrodes comprises etching through the top silicon layer and stopping on a buried oxide layer formed on a bulk silicon base substrate.

6. The method of claim 5, wherein forming the dielectric layer over the plurality of silicon electrodes comprises thermally oxidizing the plurality of silicon electrodes and the silicon interconnect.

7. The method of claim 5, further comprising:

removing a portion of the dielectric layer from over the plurality of mesa structures; and

depositing a second dielectric layer over the plurality of mesa structures.

8. The method of claim 7, wherein the second dielectric layer has a higher dielectric constant or breakdown voltage than the dielectric layer.

9. The method of claim 8, wherein the second dielectric layer is deposited with atomic layer deposition.

10. The method of claim 1 further comprising:

forming a mask layer on an SOI stack comprising;

the top silicon layer over a buried oxide layer;

a base substrate under the buried oxide layer; and

a bottom passivation layer formed under the base substrate;

etching a via opening through the bottom passivation layer, the base substrate, and the buried oxide layer; and

forming a patterned conductive layer within the via opening to make electrical contact with the silicon interconnect and the plurality of silicon electrodes.

11. The method of claim 10, further comprising thermally oxidizing side surfaces of the via opening to form a passivation layer covering the side surfaces of the via opening prior to forming the patterned conductive layer within the via opening.

12. The method of claim 11, wherein forming the dielectric layer over the plurality of silicon electrodes comprises thermally oxidizing the plurality of silicon electrodes simultaneously with thermally oxidizing the side surfaces of the via opening.

13. The method of claim 10, wherein forming the pattered conductive layer comprises depositing the patterned conductive layer through a shadow mask.

14. The method of claim 10, wherein etching the via opening through the base substrate comprises dry reactive ion etching (DRIE).

15. The method of claim 10, wherein etching the via opening through the base substrate comprises etching with a potassium hydroxide (KOH) solution to form tapered sidewalls.

16. The method of claim 10, wherein etching the via opening through the buried oxide layer comprises forming a smaller opening within the buried oxide layer than in the base substrate.

17. The method of claim 1 further comprising:

forming a mask layer on an SOI stack comprising;

the top silicon layer over a buried oxide layer;

a base substrate under the buried oxide layer; and

a bottom passivation layer formed under the base substrate; and

etching a backside via opening through the bottom passivation layer and the base substrate, stopping on the buried oxide layer; and

etching a topside via opening through the dielectric layer, the silicon layer, and the buried oxide layer;

wherein the topside via opening connects with the backside via opening.

18. The method of claim 17, further comprising depositing a patterned conductive layer within the topside via opening over an exposed top surface of the silicon interconnect and within an interior side surface of the silicon interconnect.

19. The method of claim 18, further comprising depositing a second patterned conductive layer within the backside via opening and in electrical contact with the patterned conductive layer.

20. The method of claim 18, wherein depositing the patterned conductive layer and the second patterned conductive layer comprises depositing through shadow masks.