Digital peak detector with follower mode

• US 9,035,636 B2
• Filed: 09/17/2013
• Issued: 05/19/2015
• Est. Priority Date: 09/17/2013
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Colbeck, Roger, Del Pup, Lino
• Primary Examiner(s): Pham, Emily P
• Application Number:
  US14/028,793
• Publication Number:
  US 20150078050A1
• Time in Patent Office: 609 Days
• Field of Search: 323/282, 323/283, 323/285
• US Class Current: 323/282
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 7/066 particular circuits having a special characteristic
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Circuits and processes for detecting a peak value of an input signal are disclosed. In one example, a peak detector circuit may sample a line sense signal, determine the peak value of the line sense signal during a search window, and output a peak detection signal representative of the determined peak value. In a first mode, the peak detector circuit may cause the peak detection signal to be representative of the determined peak value from an immediately preceding search window. In a second mode, the peak detector circuit may cause the peak detection signal to follow the sampled line sense signal. The peak detector circuit may operate in the second mode in response to the sample of the line sense signal being greater than a peak value of the line sense signal from an immediately preceding search window by more than a threshold amount.

Claims

1. A digital peak detection circuit for use in a controller of a power converter, the digital peak detection circuit comprising:

an input to be coupled to receive a digital sample of a line sense signal that is representative of an input voltage of the power converter;

a first comparison circuit coupled to compare the digital sample with a present maximum signal representing a maximum value of the line sense signal for a presently occurring search window and, in response to the digital sample exceeding the present maximum signal, update the present maximum signal;

a second comparison circuit coupled to compare the present maximum signal with a peak value of the line sense signal from an immediately preceding search window and output an output signal, wherein in response to the present maximum signal being greater than the peak value of the line sense signal from the immediately preceding search window by more than a threshold amount, the second comparison circuit causes the output signal to follow the present maximum signal until an end of the presently occurring search window, and wherein in response to the present maximum signal not being greater than the peak value of the line sense signal from the immediately preceding search window by more than the threshold amount, the second comparison circuit causes the output signal to represent the peak value of the line sense signal from the immediately preceding search window.

2. The digital peak detection circuit of claim 1, wherein a duration of each search window is approximately one half of a line cycle of the line sense signal.

3. The digital peak detection circuit of claim 1, wherein the first comparison circuit is further coupled to maintain the present maximum signal in response to the digital sample not being greater than the present maximum signal.

4. The digital peak detection circuit of claim 1, wherein the input is coupled to receive a digital line sense signal comprising the digital sample of the line sense signal.

5. The digital peak detection circuit of claim 4, wherein the first comparison circuit is further coupled to receive an indicator signal and update the present maximum signal in response to the digital line sense signal and the indicator signal.

6. The digital peak detection circuit of claim 1, wherein the second comparison circuit is further coupled to output a minimum voltage signal in response to the output signal being less than a minimum voltage.

7. A digital peak detection circuit for use in a controller of a power converter, the digital peak detection circuit configured to:

receive a digital sample of a line sense signal that is representative of an input voltage of the power converter;

update a present maximum signal based on the digital sample of the line sense signal, wherein the present maximum signal represents a maximum value of the line sense signal for a presently occurring search window;

in response to the present maximum signal being greater than a peak value of the line sense signal from an immediately preceding search window by more than a threshold amount, output a peak detection signal that follows the present maximum signal until an end of the presently occurring search window; and

in response to the present maximum signal not being greater than the peak value of the line sense signal from the immediately preceding search window by more than the threshold amount, output a peak detection signal representing the peak value of the line sense signal from the immediately preceding search window.

8. The digital peak detection circuit of claim 7, wherein updating the present maximum signal based on the digital sample of the line sense signal comprises:

in response to the digital sample of the line sense signal being greater than the present maximum signal, replacing the present maximum signal with the digital sample of the line sense signal; and

in response to the digital sample of the line sense signal not being greater than the present maximum signal, maintaining the present maximum signal.

9. The digital peak detection circuit of claim 7, further comprising a digital filter coupled to receive the peak detection signal and output a filtered version of the peak detection signal.

10. The digital peak detection circuit of claim 7, wherein receiving the digital sample of the line sense signal comprises receiving a digital line sense signal comprising the digital sample of the line sense signal, and wherein the digital peak detection circuit comprises:

a zero crossing detection circuit coupled to receive the digital line sense signal, wherein the zero crossing detection circuit is configured to output a pulse in an indicator signal in response to a rising edge of the digital line sense signal reaching a detection threshold value;

a running maximum finder circuit coupled to receive the digital line sense signal and the indicator signal, wherein the running maximum finder circuit is configured to update the present maximum signal based on the digital line sense signal and the indicator signal; and

a peak output circuit coupled to receive the indicator signal and the present maximum signal, wherein the peak output circuit is configured to output the peak detection signal.

11. The digital peak detection circuit of claim 7, wherein receiving the digital sample of the line sense signal comprises receiving a digital line sense signal comprising the digital sample of the line sense signal, and wherein the digital peak detection circuit comprises:

a zero crossing detection circuit coupled to receive the digital line sense signal, wherein the zero crossing detection circuit is configured to output a pulse in an indicator signal in response to a falling edge of the digital line sense signal reaching a detection threshold value;

a running maximum finder circuit coupled to receive the digital line sense signal and the indicator signal, wherein the running maximum finder circuit is configured to update the present maximum signal based on the digital line sense signal and the indicator signal; and

a peak output circuit coupled to receive the indicator signal and the present maximum signal, wherein the peak output circuit is configured to output the peak detection signal.

12. The digital peak detection circuit of claim 11 wherein the immediately preceding search window and the presently occurring search window are bound by pairs of consecutive pulses in the indicator signal.

13. The digital peak detection circuit of claim 11, wherein the peak output circuit comprises:

a memory configured to store the peak value of the line sense signal from the immediately preceding search window, wherein the memory is coupled to receive the present maximum signal and the indicator signal, and wherein the memory is further configured to replace the peak value of the line sense signal from the immediately preceding search window with a value of the present maximum signal in response to the pulse in the indicator signal;

a follower mode detection circuit coupled to receive the present maximum signal and the peak value of the line sense signal from the immediately preceding search window, wherein the follower mode detection circuit is configured to output a follower mode signal in response to a difference between the present maximum signal and the peak value of the line sense signal from the immediately preceding search window being greater than a follower threshold;

a selection circuit coupled to receive the present maximum signal, the peak value of the line sense signal from the immediately preceding search window, and the follower mode signal, wherein the selection circuit is configured to;

output the present maximum signal in response to the follower mode signal having a first value; and

output the peak value of the line sense signal from the immediately preceding search window in response to the follower mode signal having a second value; and

a peak update circuit coupled to receive an output of the selection circuit, wherein the peak update circuit is configured to;

compare the output of the selection circuit with a minimum peak voltage; and

output a greater of the minimum peak voltage and the output of the selection circuit as the peak detection signal.

14. The digital peak detection circuit of claim 11, wherein the zero crossing detection circuit comprises:

a refresh timer configured to limit a maximum duration between consecutive pulses of the indicator signal; and

a lockout timer configured to limit a minimum duration between said consecutive pulses of the indicator signal.

15. The digital peak detection circuit of claim 7, wherein the digital peak detection circuit is coupled to receive the digital sample of the line sense signal from an analog-to-digital converter coupled to receive the line sense signal.

16. The digital peak detection circuit of claim 7, wherein the analog-to-digital converter is coupled to receive a first clock signal from a clock generator, and wherein the digital peak detection circuit is coupled to receive a second clock signal from the clock generator.

17. A power converter comprising:

an output sense circuit configured to output a feedback signal representative of an output of the power converter; and

a controller coupled to receive the feedback signal, wherein the controller comprises;

a digital peak detection circuit configured to;

receive a digital sample of a line sense signal that is representative of an input voltage of the power converter;

update a present maximum signal based on the digital sample of the line sense signal, wherein the present maximum signal represents a maximum value of the line sense signal for a presently occurring search window;

in response to the present maximum signal being greater than a peak value of the line sense signal from an immediately preceding search window by more than a threshold amount, output a peak detection signal that follows the present maximum signal until an end of the present search window; and

in response to the present maximum signal not being greater than the peak value of the line sense signal from the immediately preceding search window by more than the threshold amount, output a peak detection signal representing the peak value of the line sense signal from the immediately preceding search window; and

a drive circuit coupled to receive the peak detection signal and the feedback signal, wherein the drive circuit is configured to output a drive signal for controlling a power switch based at least in part on the peak detection signal and the feedback signal.

18. The power converter of claim 17, wherein the digital peak detection circuit includes a digital filter coupled to receive the peak detection signal and output a filtered version of the peak detection signal.

19. The power converter of claim 17, wherein updating the present maximum signal based on the digital sample of the line sense signal comprises:

in response to the digital sample of the line sense signal being greater than the present maximum signal, replacing the present maximum signal with the digital sample of the line sense signal; and

in response to the digital sample of the line sense signal not being greater than the present maximum signal, maintaining the present maximum signal.

20. The power converter of claim 17, wherein receiving the digital sample of the line sense signal comprises receiving a digital line sense signal comprising the digital sample of the line sense signal, and wherein the digital peak detection circuit comprises:

a zero crossing detection circuit coupled to receive the digital line sense signal, wherein the zero crossing detection circuit is configured to output a pulse in an indicator signal in response to a rising edge of the digital line sense signal reaching a detection threshold value;

a running maximum finder circuit coupled to receive the digital line sense signal and the indicator signal, wherein the running maximum finder circuit is configured to update the present maximum signal based on the digital line sense signal and the indicator signal; and

a peak output circuit coupled to receive the indicator signal and the present maximum signal, wherein the peak output circuit is configured to output the peak detection signal.

21. The power converter of claim 17, wherein receiving the digital sample of the line sense signal comprises receiving a digital line sense signal comprising the digital sample of the line sense signal, and wherein the digital peak detection circuit comprises:

a zero crossing detection circuit coupled to receive the digital line sense signal, wherein the zero crossing detection circuit is configured to output a pulse in an indicator signal in response to a falling edge of the digital line sense signal reaching a detection threshold value;

a running maximum finder circuit coupled to receive the digital line sense signal and the indicator signal, wherein the running maximum finder circuit is configured to update the present maximum signal based on the digital line sense signal and the indicator signal; and

a peak output circuit coupled to receive the indicator signal and the present maximum signal, wherein the peak output circuit is configured to output the peak detection signal.

22. The power converter of claim 21, wherein the peak output circuit comprises:

a memory configured to store the peak value of the line sense signal from the immediately preceding search window, wherein the memory is coupled to receive the present maximum signal and the indicator signal, and wherein the memory is further configured to replace the peak value of the line sense signal from the immediately preceding search window with a value of the present maximum signal in response to a pulse in the indicator signal;

a follower mode detection circuit coupled to receive the present maximum signal and the peak value of the line sense signal from the immediately preceding search window, wherein the follower mode detection circuit is configured to output a follower mode signal in response to a difference between the present maximum signal and the peak value of the line sense signal from the immediately preceding search window being greater than a follower threshold;

a selection circuit coupled to receive the present maximum signal, the peak value of the line sense signal from the immediately preceding search window, and the follower mode signal, wherein the selection circuit is configured to;

output the present maximum signal in response to the follower mode signal having a first value; and

output the peak value of the line sense signal from the immediately preceding search window in response to the follower mode signal having a second value; and

a peak update circuit coupled to receive an output of the selection circuit, wherein the peak update circuit is configured to;

compare the output of the selection circuit with a minimum peak voltage; and

output a greater of the minimum peak voltage and the output of the selection circuit as the peak detection signal.

23. The power converter of claim 21, wherein the zero crossing detection circuit comprises:

a refresh timer configured to limit a maximum duration between consecutive pulses of the indicator signal; and

a lockout timer configured to limit a minimum duration between said consecutive pulses of the indicator signal.

24. The power converter of claim 17, further comprising an analog-to-digital converter coupled to receive the line sense signal, wherein the digital peak detection circuit is coupled to receive the digital sample of the line sense signal from the analog-to-digital converter.

25. The power converter of claim 24, further comprising a clock generator, wherein the analog-to-digital converter is coupled to receive a first clock signal from the clock generator, and wherein the digital peak detection circuit is coupled to receive a second clock signal from the clock generator.

26. A method for determining a peak value of an input signal, the method comprising:

receiving a digital sample of a line sense signal that is representative of an input voltage of a power converter;

updating a present maximum signal based on the digital sample of the line sense signal, wherein the present maximum signal represents a maximum value of the line sense signal for a presently occurring search window;

in response to the present maximum signal being greater than a peak value of the line sense signal from an immediately preceding search window by more than a threshold amount, outputting a peak detection signal that follows the present maximum signal until an end of the presently occurring search window; and

in response to the present maximum signal not being greater than the peak value of the line sense signal from the immediately preceding search window by more than the threshold amount, outputting a peak detection signal representing the peak value of the line sense signal from the immediately preceding search window.

27. The method of claim 26, wherein updating the present maximum signal based on the digital sample of the line sense signal comprises:

in response to the digital sample of the line sense signal being greater than the present maximum signal, replacing the present maximum signal with the digital sample of the line sense signal; and

in response to the digital sample of the line sense signal not being greater than the present maximum signal, maintaining the present maximum signal.

28. The method of claim 26, wherein receiving the digital sample of the line sense signal comprises receiving a digital line sense signal comprising the digital sample of the line sense signal, and wherein the immediately preceding search window and the presently occurring search window are bound by occurrences of a falling edge of the digital line sense signal reaching a detection threshold value.

29. The method of claim 26, wherein receiving the digital sample of the line sense signal comprises receiving a digital line sense signal comprising the digital sample of the line sense signal, and wherein the method further comprises:

detecting a present search window in response to a falling edge of the digital line sense signal reaching a detection threshold value; and

setting the peak value of the line sense signal from the immediately preceding search window to the present maximum signal in response to detecting the end of the presently occurring search window.

30. The method of claim 29, further comprising:

receiving a second digital sample of the line sense signal;

updating the present maximum signal based on the second digital sample of the line sense signal;

in response to the present maximum signal being greater than the peak value of the line sense signal from the immediately preceding search window by more than the threshold amount, outputting the peak detection signal that follows the present maximum signal until the end of the presently occurring search window; and

in response to an updated present maximum signal not being greater than the peak value of the line sense signal from the immediately preceding search window by more than the threshold amount, outputting the peak detection signal representing the peak value of the line sense signal from the immediately preceding search window.