Method of in-process intralayer yield detection, interlayer shunt detection and correction
First Claim
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1. A method for in-process yield evaluation in an array type of device, comprising:
- measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and
analyzing the measured electrical property to identifyinterlayer shunt defects;
wherein interlayer shunt defects are identified through a process including;
measuring electrical resistance between individual DATA lines and the GATE bus I/O pad to obtain electrical resistance data, andanalyzing the measured electrical resistance data to identify interlayer shunt defects.
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Abstract
A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
166 Citations
30 Claims
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1. A method for in-process yield evaluation in an array type of device, comprising:
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measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical property to identify interlayer shunt defects; wherein interlayer shunt defects are identified through a process including; measuring electrical resistance between individual DATA lines and the GATE bus I/O pad to obtain electrical resistance data, and analyzing the measured electrical resistance data to identify interlayer shunt defects. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for in-process yield evaluation in an array type of device, comprising:
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measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical property to identify at least one of the following; GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects; wherein the electrical property is electrical resistance; wherein GATE line open defects are identified through a process including; measuring electrical resistance between individual GATE lines and a GATE bus I/O pad, and analyzing the measured electrical resistance data to identify GATE line open defects; wherein the GATE line bridge defects are identified through a process including; measuring electrical resistance between individual GATE lines, and analyzing the measured electrical resistance data to identify GATE line bridge defects; wherein DATA line open defects are identified through a process including; measuring electrical resistance between individual DATA lines and the DATA bus I/O pad, and analyzing the measured electrical resistance data to identify DATA line open defects; wherein the DATA line bridge defects are identified through a process including; measuring electrical resistance between individual DATA lines, and analyzing the measured electrical resistance data to identify DATA line bridge defects; and wherein interlayer shunt defects are identified through a process including; measuring electrical resistance between individual DATA lines and the GATE bus I/O pad, and analyzing the measured electrical resistance data to identify interlayer shunt defects. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for in-process correction of defects in an array type of substrate, comprising:
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obtaining (i) identified defects types, including GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects, (ii) locations, and (iii) process state by a system controller; receiving by a mushroom metal and VIA layer definition module from the system controller, the identified defect types, locations, and process state; dynamically reconfiguring a die or chip design to account for defects on the substrate based at least partially on the received defect types, locations, and process state for a printing by a digital lithography printer. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A system for in-process yield evaluation for an array type of device, comprising:
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a system controller; and an electrical measurement device, operatively connected to the system controller; wherein the electrical measurement device measures an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad on the array type of device; wherein the system controller analyzes the measured electrical property to identify interlayer shunt defects; wherein the electrical measurement device measures electrical resistance between individual DATA lines and the GATE bus I/O pad to obtain electrical resistance data, and wherein the system controller analyzes the measured electrical resistance data to identify interlayer shunt defects. - View Dependent Claims (23, 24)
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25. A system for in-process yield evaluation for an array type of device, comprising:
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a system controller; and an electrical measurement device, operatively connected to the system controller; wherein the electrical measurement device measures an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad on the array type of device; and wherein the system controller analyzes the measured electrical property to identify at least one of the following on the array type of device; GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects; wherein the electrical property is electrical resistance; wherein the system controller, operatively connected to the electrical measurement device, detects GATE line open defects through a process including; measuring electrical resistance between individual GATE lines and a GATE bus I/O pad, and analyzing the measured electrical resistance data to identify GATE line open defects; wherein the GATE line bridge defects are identified through a process including; measuring electrical resistance between individual GATE lines, and analyzing the measured electrical resistance data to identify GATE line bridge defects; wherein DATA line open defects are identified through a process including; measuring electrical resistance between individual DATA lines and the DATA bus I/O pad, and analyzing the measured electrical resistance data to identify DATA line open defects; wherein the DATA line bridge defects are identified through a process including; measuring electrical resistance between individual DATA lines, and analyzing the measured electrical resistance data to identify DATA line bridge defects; and wherein interlayer shunt defects are identified through a process including; measuring electrical resistance between individual DATA lines and the GATE bus I/O pad, and analyzing the measured electrical resistance data to identify interlayer shunt defects.
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26. A system for in-process correction of defects in an array type of substrate, comprising:
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a system controller configured to obtain (i) identified defects types, including GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects, (ii) locations, and (iii) process state; a mushroom metal and VIA layer definition module; and a digital lithography printer; wherein the mushroom metal and VIA layer definition module receives the defect data from the system controller, where the defect data comprises; identified defect types, defect locations, and a process state; and wherein the mushroom metal and via layer definition module dynamically reconfigures a die or chip design to account for defects on the substrate based at least partially on the received defect types, locations, and process state. - View Dependent Claims (27, 28)
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29. A method for in-process yield evaluation in an array type of device, comprising:
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measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical property to identify at least one of the following; GATE line open defects, and DATA line open defects; wherein GATE line open defects are identified through a process including; measuring electrical resistance between individual GATE lines and a GATE bus I/O pad, and analyzing the measured electrical resistance data to identify GATE line open defects; wherein DATA line open defects are identified through a process including; measuring electrical resistance between individual DATA lines and the DATA bus I/O pad, and analyzing the measured electrical resistance data to identify DATA line open defects.
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30. A system for in-process yield evaluation for an array type of device, comprising:
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a system controller; and an electrical measurement device, operatively connected to the system controller; wherein the electrical measurement device measures an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad on the array type of device; wherein the system controller analyzes the measured electrical property to identify at least one of the following on the array type of device; GATE line open defects, and DATA line open defects; wherein GATE line open defects are identified through a process including; measuring electrical resistance between individual GATE lines and a GATE bus I/O pad, and analyzing the measured electrical resistance data to identify GATE line open defects; and wherein DATA line open defects are identified through a process including; measuring electrical resistance between individual DATA lines and the DATA bus I/O pad, and analyzing the measured electrical resistance data to identify DATA line open defects.
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Specification