Resistive memory array and method for controlling operations of the same

• US 9,036,397 B2
• Filed: 09/21/2012
• Issued: 05/19/2015
• Est. Priority Date: 04/02/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chien, Wei-Chih, Lee, Ming-Hsiu, Lee, Feng-Ming
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huerta, Pablo
• Application Number:
  US13/624,761
• Publication Number:
  US 20130028005A1
• Time in Patent Office: 970 Days
• Field of Search: 365/148
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/51 Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. A resistive memory array including an array of the above resistive memory units, word lines and bit lines is also described, wherein the word (bit) lines are coupled to the first (second) memory layers.

Claims

1. A resistive memory array, comprising:

a plurality of resistive memory units arranged in rows and columns, wherein each of the resistive memory units comprises a first memory cell, and a second memory cell disposed under and electrically connected in series with the first memory cell, wherein each of the resistive memory units includes;

a first solid electrolyte, being a part of the first memory cell;

a second solid electrolyte, being a part of the second memory cell; and

an oxidizable electrode, formed between the first solid electrolyte and the second solid electrolyte,

wherein the first solid electrolyte and the second solid electrolyte are made of a transition metal oxide or a material containing at least one chalcogenide element;

a plurality of word lines, wherein each of the word lines is coupled to the first memory cells of a row of the resistive memory units; and

a plurality of bit lines, wherein each of the bit lines is coupled to the second memory cells of a column of the resistive memory units.

2. The resistive memory array of claim 1, wherein the oxidizable electrode is made of a material selected from the group consisting of silver, copper and zinc.

3. The resistive memory array of claim 1, further comprising:

a composing layer having two silicon oxide spacers and a tungsten layer formed between the two silicon oxide spacers, wherein the second solid electrolyte is formed between the oxidizable electrode and the composing layer.

4. The resistive memory array of claim 3, further comprising:

a titanium nitride layer, an inter-metal dielectric (IMD) layer, and a substrate, wherein the titanium nitride layer is formed between the composing layer and the IMD layer, and the IMD layer is formed between the titanium nitride layer and the substrate.

5. A method for controlling operations of a resistive memory array of claim 1, comprising:

(a) selecting, via a word line and a bit line, a resistive memory unit to be operated; and

(b) measuring a resistance of the selected resistive memory unit and determining which one of a first state, a second state and a third state is a state of the selected resistive memory unit according to the measured resistance.

6. The method of claim 5, wherein the step (b) comprises:

measuring the resistance as a first resistance by applying a first voltage to the selected resistive memory unit;

determining that the state of the resistive memory unit is the first state when the first resistance is equal to a predetermined value;

when the first resistance is different from the predetermined value, measuring the resistance as a second resistance by applying a second voltage to the selected resistive memory unit; and

determining that the state of the selected resistive memory unit is the second state when the second resistance is equal to the first resistance, or determining that the state of the selected resistive memory unit is the third state when the second resistance is not equal to the first resistance.

7. The method of claim 6, further comprising:

reprogramming the selected resistive memory unit to be at the third state when the state of the selected resistive memory unit is determined as the third state.

8. The method of claim 7, wherein the first voltage is less than the second voltage.

9. A resistive memory array, comprising:

a plurality of resistive memory units arranged in rows and columns, wherein each of the resistive memory units comprises a first memory cell, and a second memory cell disposed under and electrically connected in series with the first memory cell, wherein each of the resistive memory units includes;

a first barrier layer;

a second barrier layer; and

a metal oxide layer, formed between the first barrier layer and the second barrier layer;

wherein a first active region is between the first barrier layer and the metal oxide layer and is a part of the first memory cell, and a second active region is between the second barrier layer and the metal oxide layer and is a part of the second memory cell;

a plurality of word lines, wherein each of the word lines is coupled to the first memory cells of a row of the resistive memory units; and

a plurality of bit lines, wherein each of the bit lines is coupled to the second memory cells of a column of the resistive memory units.

10. The resistive memory array of claim 9, wherein the first barrier layer and the second barrier layer are made of a material selected from a group consisting of titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), and gold (Au), and the metal oxide layer is made of a material selected from a group consisting of tungsten oxide, titanium oxide, nickel oxide, aluminum oxide, cupric oxide, zirconium oxide, niobium oxide, and tantalum oxide.

11. The resistive memory array of claim 9, wherein each of the first active region and the second active region has two resistive states.

12. The resistive memory array of claim 9, further comprising:

two silicon oxide spacers, a first electrode, a second electrode, an inter-metal dielectric (IMD) layer, and a substrate, wherein the two silicon oxide spacers are contacted with the metal oxide layer and formed between the first barrier layer and the second barrier layer, the first electrode is formed on the first barrier layer, the second electrode is formed between the second barrier layer and the IMD layer, and the IMD layer is formed between the second electrode and the substrate.

13. The resistive memory array of claim 12, wherein the first electrode and the second electrode are made of an aluminum-copper alloy.

14. A method for controlling operations of a resistive memory array of claim 9, comprising:

(a) programming the resistive memory array such that in each of the resistive memory units, the first memory cell and the second memory cell are not simultaneously at low-resistance states;

(b) selecting, via a word line and a bit line, a memory unit to be operated; and

(c) measuring a resistance of the selected resistive memory unit, and determining which one of a first state and a second state is a state of the selected resistive memory unit according to the measured resistance.

15. The method of claim 14, wherein the step (c) comprises:

measuring the resistance as a read resistance by applying a read voltage to the selected resistive memory unit; and

determining that the state of the selected resistive memory unit is the first state when the read resistance is equal to a predetermined value, or determining that the state of the selected resistive memory unit is the second state when the read resistance is not equal to the predetermined value.

16. The method of claim 15 further comprising:

reprogramming the selected resistive memory unit to be at the second state when the state of the selected resistive memory unit is determined as the second state.