Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same

• US 9,036,421 B2
• Filed: 02/12/2014
• Issued: 05/19/2015
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Zengtao
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US14/178,526
• Publication Number:
  US 20140160850A1
• Time in Patent Office: 461 Days
• Field of Search: 365/185.01, 365/185.11, 365/185.14, 365/185.17
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Claims

1. An electronic system, comprising:

controlling circuitry; and

a memory device coupled to the controlling circuitry;

wherein the memory device comprises a string of memory cells; and

wherein a single string select gate is configured to concurrently selectively couple a first end of the string of memory cells to a data line and a second end of the string of memory cells to a source line.

2. The electronic system of claim 1, wherein the string of memory cells comprises a first vertical portion of memory cells and a second vertical portion of memory cells.

3. The electronic system of claim 2, wherein the first end of the string of memory cells is at an uppermost end of the first vertical portion of memory cells and the second end of the string of memory cells is at an uppermost end of the second vertical portion of memory cells.

4. The electronic system of claim 2, wherein a plane gate is configured to selectively couple the first and second vertical portions of memory cells.

5. The electronic system of claim 2, wherein the first and second vertical portions of memory cell share a channel.

6. The electronic system of claim 1, further comprising a first select gate coupled to the first end of the string and a second select gate coupled to the second end of the string.

7. The electronic system of claim 6, wherein the string select gate is configured to selectively couple the first select gate to the data line and the second select gate to the source line.

8. The electronic system of claim 1, wherein the string select gate is formed between the first end of the string of memory cells and the second end of the string of memory cells.

9. The electronic system of claim 1, wherein the controlling circuitry controls operations on the string of memory cells.

10. The electronic system of claim 9, wherein the operations include data read, data program, and erase operations.

11. The electronic system of claim 1, further comprising an interface through which the controlling circuitry is coupled to the memory device.

12. The electronic system of claim 11, wherein the interface is selected from the group consisting of a USB interface, a SATA interface, and a PATA interface.

13. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, the memory device comprising;

a first vertical stack of memory cells; and

a second vertical stack of memory cells adjacent to the first vertical stack of memory cells;

wherein a single string select gate is configured to selectively couple the first vertical stack of memory cells to a data line and to concurrently selectively couple the second vertical stack of memory cells to a source line.

14. The electronic system of claim 13, wherein the first vertical stack of memory cells and the second vertical stack of memory cells are coupled together.

15. The electronic system of claim 13, wherein a plane gate selectively couples the first vertical stack of memory cells and the second vertical stack of memory cells together.

16. The electronic system of claim 13, wherein the first vertical stack of memory cells and the second vertical stack of memory cells share a continuous channel.

17. The electronic system of claim 13, further comprising a first select gate coupled to an uppermost memory cell of the first vertical stack of memory cells and a second select gate coupled to an uppermost memory cell of the second vertical stack of memory cells.

18. The electronic system of claim 17, wherein the string select gate is configured to selectively couple the first select gate to the data line and the second select gate to the source line.

19. An electronic system, comprising:

a processor; and

a memory device, memory device comprising;

a memory array; and

control circuitry coupled to the processor, wherein the control circuitry is configured to receive commands from the processor that control operations on the memory array;

wherein the memory array comprises;

a first column of memory cells formed vertically over a semiconductor;

a second column of memory cells formed vertically over the semiconductor and adjacent to the first column of memory cells;

wherein a single string select gate is configured to selectively couple the first column to a data line and to concurrently selectively couple the second column to a source line.

20. The electronic system of claim 19, wherein the memory device further comprises address circuitry coupled to the memory array and coupled to receive addresses from the processor and input/output circuitry coupled to the memory array and coupled to receive data from and to transmit data to the processor.