Memory cell sensing using a boost voltage

• US 9,036,426 B2
• Filed: 12/18/2013
• Issued: 05/19/2015
• Est. Priority Date: 06/02/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Moschiano, Violante, Di Cicco, Domenico, D'Alessandro, Andrea
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/132,124
• Publication Number:
  US 20140177342A1
• Time in Patent Office: 517 Days
• Field of Search: 365/185.25, 365/185.18, 365/185.21
• US Class Current: 365/185.25
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure

Abstract

The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.

Claims

1. A device, comprising:

an array of memory cells; and

a controller configured to;

pre-charge and/or float a data line associated with a selected memory cell of the array;

apply a positive boost voltage to a source associated with the selected memory cell after the data line is pre-charged and/or floating, wherein the source is associated with a plurality of strings of memory cells of the array, and wherein one of the plurality of strings includes the selected memory cell; and

determine a state of the selected memory cell based on a sensed discharge of the data line after applying the positive boost voltage to the source.

2. The device of claim 1, wherein the controller includes sense circuitry.

3. The device of claim 1, wherein the controller is further configured to increase a tub region and/or a well region of a semiconductor substrate in which the array is formed to the boost voltage.

4. The device of claim 1, wherein the controller is further configured to apply a ground voltage to a tub region and/or a well region of a semiconductor substrate in which the array is formed.

5. The device of claim 1, wherein:

the selected memory cell has a negative threshold voltage; and

the controller is configured to determine the state of the selected memory cells without applying a negative voltage to the selected memory cell.

6. A device, comprising:

an array of memory cells, wherein the array includes a plurality of strings of memory cells; and

a controller configured to;

pre-charge a data line associated with a selected memory cell of the array to a positive pre-charge voltage;

float the pre-charged data line;

apply a positive boost voltage to a source associated with the selected memory cell after floating the pre-charged data line, wherein the source is associated with the plurality of strings and one of the plurality of strings includes the selected memory cell;

cause a discharge of the source after applying the positive boost voltage to the source; and

determine a state of the selected memory cell based on a sensed discharge of the data line in response to the discharge of the source.

7. The device of claim 6, wherein the controller does not include negative voltage sense circuitry.

8. The device of claim 6, wherein:

the selected memory cell has a drain select gate and a source select gate associated therewith; and

the controller is further configured to apply a voltage to the drain select gate and the source select gate while causing the discharge of the source.

9. The device of claim 8, wherein the voltage applied to the drain select gate and the source select gate is greater than a sum of the positive pre-charge voltage and the positive boost voltage.

10. The device of claim 8, wherein the voltage applied to the drain select gate and the source select gate is equal to a sum of the positive boost voltage and a select gate voltage.

11. The device of claim 6, wherein the controller is configured to pre-charge the data line to the positive pre-charge voltage by applying the positive pre-charge voltage to the data line.

12. A device, comprising:

an array of memory cells; and

a controller configured to;

pre-charge a data line associated with a selected memory cell of the array, wherein the selected memory cell has a negative threshold voltage;

boost the pre-charged data line; and

determine a state of the selected memory cell based on a sensed discharge of the data line responsive to boosting the pre-charged data line and without applying a negative voltage to the selected memory cell.

13. The device of claim 12, wherein:

the array includes an access line associated with the selected memory cell; and

the controller is configured to determine the state of the selected memory cell without applying a negative voltage to the access line.

14. The device of claim 12, wherein the negative threshold voltage is within a threshold voltage distribution that includes only negative threshold voltages.

15. The device of claim 12, wherein the negative threshold voltage is within a threshold voltage that includes positive and negative threshold voltages.

16. The device of claim 12, wherein the state of the selected memory cell is a programmed state.

17. The device of claim 12, wherein the state of the selected memory cell is an erased state.

18. The device of claim 12, wherein the negative threshold voltage is less than −

1.5 Volts.