Processor arrangement on a chip including data processing, memory, and interface elements
DCFirst Claim
Patent Images
1. A multi-processor system on a chip, comprising:
- a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data;
a plurality of memory elements that each independently operates as a cache for caching data; and
at least one interface element for providing a connection to a common higher level memory;
wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element;
wherein the bus system is adapted for dynamically establishing and releasing transmission channels between a sending one of the elements and a receiving one of the elements; and
wherein the bus system is adapted for forming at least one ring via interconnection elements that include pipeline-registers.
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Abstract
At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).
651 Citations
75 Claims
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1. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; wherein the bus system is adapted for dynamically establishing and releasing transmission channels between a sending one of the elements and a receiving one of the elements; and wherein the bus system is adapted for forming at least one ring via interconnection elements that include pipeline-registers. - View Dependent Claims (2)
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3. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; wherein the bus system is adapted for dynamically establishing and releasing transmission channels between a sending one of the elements and a receiving one of the elements; and wherein an identification token is assigned to transmitted data for indicating an affiliation of the transmitted data to a process.
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4. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; wherein the bus system is adapted for dynamically establishing and releasing transmission channels between a sending one of the elements and a receiving one of the elements; and wherein an identification token is assigned to data transferred via the interface element for indicating an affiliation of the transferred data to a process.
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5. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element, and wherein the bus system is adapted for forming at least one ring via interconnection elements that include pipeline registers. - View Dependent Claims (6)
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7. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; and wherein an identification token is assigned to transmitted data for indicating an affiliation of the transmitted data to a process.
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8. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; and wherein an identification token is assigned to data transferred via the interface element for indicating an affiliation of the transferred data to a process.
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9. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements, that each independently operates as cache for caching data; at least one interface element for providing a connection to a common higher level memory; and at least one global interconnection system adapted for interconnecting the plurality of data processing elements, the plurality of memory elements, and the at least one interface element;
wherein;the at least one global interconnection system is accessible by each of the data processing elements and memory elements via a respective dedicated bus interface node, and permits flexible allocation and interconnection during run time; transmitters and receivers of the data processing, memory and interface elements are adapted for being connected via the global interconnection system in an addressed manner to permit individual data transfer; and each of the data processing elements, memory elements, and at least one interface element are separately connected to the global interconnection system for transferring data between (i) at least one of the data processing elements and at least one of the memory elements, and (ii) at least one of the memory elements and the at least one interface element; and further wherein at least one interface element is adapted to connect to an external peripheral and the global interconnect system is adapted to transfer data to and from said external peripheral. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements, that each independently operates as cache for caching data; at least one interface element for providing a connection to a common higher level memory; and at least one global interconnection system adapted for interconnecting the plurality of data processing elements, the plurality of memory elements, and the at least one interface element;
wherein;the at least one global interconnection system is accessible by each of the data processing elements and memory elements via a respective dedicated bus interface node, and permits flexible allocation and interconnection during run time; transmitters and receivers of the elements are adapted for being connected via the global interconnection in an addressed manner to permit individual data transfer; and each of the data processing elements, memory elements, and at least one interface element are connected to the global interconnection system for transferring data between (i) at least one of the data processing elements and at least one of the memory elements, and (ii) at least one of the memory elements and the at least one interface element; and wherein an identification token is assigned to transmitted data for indicating its affiliation of the transmitted data to a process.
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27. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements, that each independently operates as cache for caching data; at least one interface element for providing a connection to a common higher level memory; and at least one global interconnection system adapted for interconnecting the plurality of data processing elements, the plurality of memory elements, and the at least one interface element;
wherein;the at least one global interconnection system is accessible by each of the data processing elements and memory elements via a respective dedicated bus interface node, and permits flexible allocation and interconnection during run time; transmitters and receivers of the elements are adapted for being connected via the global interconnection in an addressed manner to permit individual data transfer; and each of the data processing elements, memory elements, and at least one interface element are connected to the global interconnection system for transferring data between (i) at least one of the data processing elements and at least one of the memory elements, and (ii) at least one of the memory elements and the at least one interface element; and wherein an identification token is assigned to data transferred via the interface element for indicating an affiliation of the transferred data to a process.
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28. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; wherein the bus system is adapted for dynamically establishing and releasing transmission channels between a sending one of the elements and a receiving one of the elements; wherein the data transmission is via the bus system and managed by control signals transmitted via the bus; wherein the bus system is adapted for transmitting data in at least two directions and comprises separate and independent structures for each of the data transmission directions; and wherein the bus system is adapted for forming at least one ring via interconnection elements that include pipeline-registers.
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29. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; wherein the bus system is adapted for transmitting data in at least two directions and comprises separate and independent structures for each of the data transmission directions; and wherein the bus system is adapted for forming at least one ring via interconnection elements that include pipeline-registers.
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30. A multi-processor system on a chip, comprising:
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a plurality of data processing elements that each includes at least one arithmetic-logic unit (ALU) and a plurality of registers adapted for storing data; a plurality of memory elements that each independently operates as a cache for caching data; and at least one interface element for providing a connection to a common higher level memory; wherein each of the data processing elements, each of the memory elements, and each of the at least one interface element are interconnected via a bus system for transferring data at least between (i) at least one of the data processing elements and at least one of the memory elements and (ii) at least one of the memory elements and the at least one interface element; and wherein each of the data processing elements and each of the memory elements are separately connected to the bus system; and further wherein at least one interface element is adapted to connect to an external peripheral and the bus system is adapted to transfer data to and from said external peripheral. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
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Specification