Method, apparatus and system for memory validation

• US 9,037,812 B2
• Filed: 11/17/2011
• Issued: 05/19/2015
• Est. Priority Date: 11/17/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chew, Yen Hsiang
• Primary Examiner(s): Ruiz, Aracelis
• Application Number:
  US13/997,509
• Publication Number:
  US 20130275691A1
• Time in Patent Office: 1,279 Days
• Field of Search: 711/154
• US Class Current: 711/154
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

Techniques and mechanisms for assuring that one or more addressable locations in memory of a computer platform are transitioned from potentially invalid state to known-valid state. In an embodiment, a memory validation agent separate from a processor of the computer platform performs memory validation writes in response to an indication of power state transition. In another embodiment, the memory validation agent determines information to be included in write commands which implement the memory validation, where the determining the information is decoupled from operation of the processor.

Claims

1. An apparatus comprising:

a memory validation agent to operate in a computer platform, wherein the memory validation agent to couple to a processor of the computer platform, the memory validation agent including;

write logic to access a memory device of the computer platform; and

control logic to detect a signal sent to the memory validation agent, the signal indicating a transition of the computer platform from a first power state, where data in the memory device of the computer platform is allowed to degrade while the computer platform is in the first power state, the control logic further to cause the write logic to perform a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state.

2. The apparatus of claim 1, wherein the apparatus includes a memory controller, and wherein the memory validation agent resides in the memory controller.

3. The apparatus of claim 1, wherein the write logic to perform the plurality of writes comprises:

the write logic to generate a plurality of write commands, wherein the memory validation agent to determine command information to include in respective ones of the write command, wherein determination of the command information is decoupled from operation of the processor.

4. The apparatus of claim 3, the memory validation agent to determine the command information includes the memory validation agent to determine a value to be written to a location of the memory device, wherein the memory validation agent to determine the value is independent of the processor specifying the value to the memory validation agent after the power state transition.

5. The apparatus of claim 4, wherein the memory validation agent to determine the value includes one of:

a random number generator to provide the value; and

the memory validation agent to access information describing a deterministic process for generating the value.

6. The apparatus of claim 4, wherein the memory validation agent to determine the command information further includes the memory validation agent to determine an error correction value corresponding to the value.

7. The apparatus of claim 3, wherein the memory validation agent to determine the command information includes the memory validation agent to determine an address of a location of the memory, wherein determination of the address is independent of the processor specifying the address to the memory validation agent after the power state transition.

8. A method comprising:

detecting at a memory validation agent of a computer platform a signal sent to the memory validation agent, the memory validation agent coupled to a processor of the computer platform, the signal indicating a transition of the computer platform from a first power state, where data in a memory device of the computer platform is allowed to degrade while the computer platform is in the first power state; and

performing, with the memory validation agent, a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state.

9. The method of claim 8, wherein performing the plurality of writes comprises:

generating a plurality of write commands, including determining command information to include in respective ones of the write command, wherein determining the command information is decoupled from operation of the processor.

10. The method of claim 9, wherein determining the command information includes determining a value to be written to a location of the memory device, wherein determining the value is independent of the processor specifying the value to the memory validation agent after the power state transition.

11. The method of claim 10, determining the value includes one of:

a random number generator providing the value; and

accessing information describing a deterministic process for generating the value.

12. The method of claim 10, wherein determining the command information further includes determining an error correction value corresponding to the value.

13. The method of claim 9, wherein determining the command information includes determining an address of a location of the memory, wherein determining the address is independent of the processor specifying the address to the memory validation agent after the power state transition.

14. The method of claim 8, wherein the plurality of writes are before any loading of firmware interface code or boot code into the memory device after the power state transition.

15. A computer system comprising:

a processor to perform one or more initialization processes in support of a transition by the computer system from a first power state;

a memory validation agent coupled to the processor, the memory validation agent including;

write logic to access a memory device of the computer platform;

control logic to detect a signal sent from the processor to the memory validation agent, the signal indicating the transition by the computer platform from the first power state, where data in the memory device of the computer platform is allowed to degrade while the computer platform is in the first power state, the control logic further to cause the write logic to perform a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state; and

a wireless network interface including one or more antennae to exchange a communication between the computer system and a network.

16. The computer system of claim 15, further comprising a memory controller, and wherein the memory validation agent resides in the memory controller.

17. The computer system of claim 15, wherein the write logic to perform the plurality of writes comprises:

the write logic to generate a plurality of write commands, wherein the memory validation agent to determine command information to include in respective ones of the write command, wherein determination of the command information is decoupled from operation of the processor.

18. The computer system of claim 17, the memory validation agent to determine the command information includes the memory validation agent to determine a value to be written to a location of the memory device, wherein the memory validation agent to determine the value is independent of the processor specifying the value to the memory validation agent after the power state transition.

19. The computer system of claim 18, wherein the memory validation agent to determine the value includes one of:

a random number generator to provide the value; and

the memory validation agent to access information describing a deterministic process for generating the value.

20. The computer system of claim 17, wherein the memory validation agent to determine the command information includes the memory validation agent to determine an address of a location of the memory, wherein determination of the address is independent of the processor specifying the address to the memory validation agent after the power state transition.