Method, apparatus and system for memory validation
First Claim
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1. An apparatus comprising:
- a memory validation agent to operate in a computer platform, wherein the memory validation agent to couple to a processor of the computer platform, the memory validation agent including;
write logic to access a memory device of the computer platform; and
control logic to detect a signal sent to the memory validation agent, the signal indicating a transition of the computer platform from a first power state, where data in the memory device of the computer platform is allowed to degrade while the computer platform is in the first power state, the control logic further to cause the write logic to perform a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state.
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Abstract
Techniques and mechanisms for assuring that one or more addressable locations in memory of a computer platform are transitioned from potentially invalid state to known-valid state. In an embodiment, a memory validation agent separate from a processor of the computer platform performs memory validation writes in response to an indication of power state transition. In another embodiment, the memory validation agent determines information to be included in write commands which implement the memory validation, where the determining the information is decoupled from operation of the processor.
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Citations
20 Claims
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1. An apparatus comprising:
a memory validation agent to operate in a computer platform, wherein the memory validation agent to couple to a processor of the computer platform, the memory validation agent including; write logic to access a memory device of the computer platform; and control logic to detect a signal sent to the memory validation agent, the signal indicating a transition of the computer platform from a first power state, where data in the memory device of the computer platform is allowed to degrade while the computer platform is in the first power state, the control logic further to cause the write logic to perform a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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detecting at a memory validation agent of a computer platform a signal sent to the memory validation agent, the memory validation agent coupled to a processor of the computer platform, the signal indicating a transition of the computer platform from a first power state, where data in a memory device of the computer platform is allowed to degrade while the computer platform is in the first power state; and performing, with the memory validation agent, a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer system comprising:
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a processor to perform one or more initialization processes in support of a transition by the computer system from a first power state; a memory validation agent coupled to the processor, the memory validation agent including; write logic to access a memory device of the computer platform; control logic to detect a signal sent from the processor to the memory validation agent, the signal indicating the transition by the computer platform from the first power state, where data in the memory device of the computer platform is allowed to degrade while the computer platform is in the first power state, the control logic further to cause the write logic to perform a plurality of writes each to a respective one of multiple addressable locations of the memory device, each of the plurality of writes in response to the detected signal, wherein the plurality of writes include an earliest write to the multiple addressable locations subsequent to the transition from the first power state; and a wireless network interface including one or more antennae to exchange a communication between the computer system and a network. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification