VCSEL packaging

• US 9,038,883 B2
• Filed: 09/07/2014
• Issued: 05/26/2015
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: Ams-Osram International GmbH (Ams-Osram AG)
• Original Assignee: Princeton Optronics Inc (Ams-Osram AG)
• Inventors: Wang, Qing, Seurin, Jean-Francois, Ghosh, Chuni Lal, Watkins, Laurence
• Primary Examiner(s): STONER, KILEY SHAWN
• Application Number:
  US14/479,325
• Publication Number:
  US 20150069113A1
• Time in Patent Office: 261 Days
• Field of Search: None
• US Class Current: 228/102
• CPC Class Codes: B23K 1/0016 Brazing of electronic components
• CPC Class Codes: B23K 1/012 Soldering with the use of hot gas
• CPC Class Codes: B23K 2101/42 Printed circuits
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01S 5/0042 On wafer testing, e.g. lasers are tested before separating wafer into chips
• CPC Class Codes: H01S 5/02345 Wire-bonding
• CPC Class Codes: H01S 5/0237 by soldering
• CPC Class Codes: H01S 5/423 having a vertical cavity
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 2201/10121 Optical component, e.g. opto-electronic component
• CPC Class Codes: H05K 2201/10727 Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 2203/085 Using vacuum or low pressure
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3494 Heating methods for reflowing of solder using integral heating means H05K1/0212
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.

Claims

1. A packaging process comprising the steps of:

positioning and aligning a submount in a vacuum soldering apparatus, wherein said submount is a thermal submount, a printed circuit board or a combination thereof;

aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the submount such that a plurality of bonding pads on the submount align substantially with corresponding plurality of contact pads on the VCSEL chip;

correcting for a curvature of the VCSEL chip surface by applying a pre-determined amount of pressure effected through a structured pad with raised regions to differentially apply controlled pressure on predetermined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature;

sealing the vacuum soldering apparatus for enclosing the submount and the VCSEL chip;

creating an air free environment in the vacuum soldering apparatus; and

heating the submount and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount.

2. The packaging process as in claim 1, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus.

4. The packaging process as in claim 1, wherein the step of applying pressure using the structured pad on the VCSEL chip surface is facilitated by one or more spacer.

5. The packaging process as in claim 1, wherein the step of applying pressure using the structured pad on the VCSEL chip surface is facilitated by a spring.

6. The packaging process as in claim 1, wherein bonding is facilitated through providing solder between plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip.

7. The packaging process as in claim 1, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding.

9. The packaging process as in claim 1, wherein air free environment is one selected from the group consisting of vacuum, inert gas and a gas providing a reducing environment.

3. A packaging process comprising the steps of:

positioning and aligning a submount in a vacuum soldering apparatus;

aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the submount such that a plurality of bonding pads on the submount align substantially with corresponding plurality of contact pads on the VCSEL chip;

measuring curvature of the VCSEL chip surface, wherein said step of measuring curvature of the VCSEL chip surface is effected through measuring an angle of reflection across the VCSEL chip surface in response to a radiation incident upon said VCSEL chip surface at a fix angle;

correcting for the curvature of the VCSEL chip surface by applying pre-determined amount of pressure;

sealing the vacuum soldering apparatus for enclosing the submount and the VCSEL chip;

creating an air free environment in the vacuum soldering apparatus; and

heating the submount and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount.

8. The packaging process as in claim 3, wherein said steps of measuring curvature and correcting for the curvature are performed iteratively in a test run loop to determine a set of pressure values suitable for the measured curvature of the VCSEL chip.

18. The packaging process as in claim 3, wherein said submount is one selected from the group consisting of a thermal submount, a printed circuit board or a combination thereof.

19. The packaging process as in claim 3, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus.

20. The packaging process as in claim 3, wherein the step of applying pressure on the VCSEL chip surface is facilitated by one or more spacers in conjunction with a spring.

21. The packaging process as in claim 3, wherein said step of applying pressure is further effected through a structured pad designed to apply pressure differentially on pre-determined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature.

22. The packaging process as in claim 3, wherein bonding is facilitated through providing solder between plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip.

23. The packaging process as in claim 3, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding.

10. A packaging process comprising the steps of:

positioning and aligning a printed circuit board in a vacuum soldering apparatus;

aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the printed circuit board such that a plurality of contact pads on the printed circuit board align substantially with corresponding plurality of contact pads on the VCSEL chip;

measuring curvature of the surface of the VCSEL chip surface, wherein said step of measuring curvature of the VCSEL chip surface is effected through measuring an angle of reflection across the VCSEL chip surface in response to a radiation incident upon said VCSEL chip surface at a fix angle;

correcting for the curvature of the VCSEL chip surface by applying pre-determined amount of pressure;

sealing the vacuum soldering apparatus for enclosing the printed circuit board and the VCSEL chip;

creating an air free environment in the vacuum soldering apparatus; and

heating the printed circuit board and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount.

11. The packaging process as in claim 10, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus.

12. The packaging process as in claim 10, wherein the step of applying pressure on the VCSEL chip surface is facilitated by one or more spacers in conjunction with a spring.

13. The packaging process as in claim 10, wherein said step of applying pressure is further effected through a structured pad designed to apply pressure differentially on pre-determined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature.

14. The packaging process as in claim 10, wherein bonding is facilitated through providing solder between plurality of bonding pads on the printed circuit board and corresponding plurality of contact pads on the VCSEL chip.

15. The packaging process as in claim 10, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding.

17. The packaging process as in claim 10, wherein air free environment is one selected from the group consisting of vacuum, inert gas and a gas providing a reducing environment.

16. A packaging process comprising the steps of:

positioning and aligning a printed circuit board in a vacuum soldering apparatus;

aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the printed circuit board such that a plurality of contact pads on the printed circuit board align substantially with corresponding plurality of contact pads on the VCSEL chip;

measuring curvature of the surface of the VCSEL chip surface, wherein said step of measuring curvature of the VCSEL chip surface is effected through measuring an angle of reflection across the VCSEL chip surface in response to a radiation incident upon said VCSEL chip surface at a fix angle;

correcting for the curvature of the VCSEL chip surface by applying pre-determined amount of pressure, wherein said steps of measuring curvature and correcting of curvature are performed iteratively in a test run loop to determine a set of pressure values suitable for the measured curvature of the VCSEL chip surface;

sealing the vacuum soldering apparatus for enclosing the printed circuit board and the VCSEL chip;

creating an air free environment in the vacuum soldering apparatus; and

heating the printed circuit board and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount.

24. The packaging process as in claim 16, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus.

25. The packaging process as in claim 16, wherein the step of applying pressure on the VCSEL chip surface is facilitated by one or more spacers in conjunction with a spring.

26. The packaging process as in claim 16, wherein said step of applying pressure is further effected through a structured pad designed to apply pressure differentially on pre-determined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature.

27. The VCSEL packaging process as in claim 16, wherein bonding is facilitated through providing solder between plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip.

28. The VCSEL packaging process as in claim 16, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding.