Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus

• US 9,040,343 B2
• Filed: 11/25/2013
• Issued: 05/26/2015
• Est. Priority Date: 10/07/2010
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Enomoto, Takayuki, Togashi, Hideaki
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US14/088,978
• Publication Number:
  US 20140080252A1
• Time in Patent Office: 547 Days
• Field of Search: 438/98
• US Class Current: 438/98
• CPC Class Codes: H01L 27/14614 having a special gate structure
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A solid-state imaging device including a substrate, a through-hole, a vertical gate electrode, and a charge fixing film. A photoelectric conversion unit generating signal charges in accordance with the amount of received light is formed in the substrate. The through-hole is formed from a front surface side through a rear surface side of the substrate. The vertical gate electrode is formed through a gate insulating film in the through-hole and reads out the signal charges generated by the photoelectric conversion unit to a reading-out portion. The charge fixing film has negative fixed charges formed to cover a portion of the inner circumferential surface of the through-hole at the rear surface side of the substrate while covering the rear surface side of the substrate.

Claims

1. A method of manufacturing a solid-state imaging device, comprising:

forming a gate insulating film lined hole with a desired depth extending from a front surface side of a substrate toward a rear surface side of the substrate;

forming a vertical gate electrode that causes a reading-out portion formed at a surface side of the substrate to read out the signal charges accumulated in a photoelectric conversion unit by embedding an electrode material into the gate insulating film lined hole;

forming a wire layer where a plurality of layers of wires are stacked, on the front surface side of the substrate in an interlayer insulating film;

turning over the substrate after bonding a support substrate onto the wire layer;

removing the gate insulating film formed in the through-hole to a predetermined depth and reducing the thickness of the substrate until the hole extends to the rear surface side of the substrate; and

forming a charge fixing film having negative fixed charges covering the entire rear surface of the substrate and filling the through-hole where the gate insulating film was removed with the charge fixing claim.

2. The method according to claim 1, wherein the substrate is a bulk substrate.

3. The method according to claim 1, wherein the substrate is an SOI substrate having a monocrystal silicon layer formed through a silicon oxide layer, on a silicon substrate.

4. The method according to claim 3, wherein the hole is formed deep such that the silicon oxide layer is exposed from the surface of the monocrystal silicon layer.

5. The method according to claim 1, wherein the reducing of the thickness of the substrate is performed by wet etching several times.

6. The method according to claim 1, wherein one or a plurality of layers of insulating films are further formed on the charge fixing film after the charge fixing film is formed.

7. The method according to claim 1, wherein the charge fixing film has a structure of stacking two or more kinds of layers.

8. A method, comprising:

providing a substrate with oppositely facing front and rear surfaces;

forming a gate insulting film lined hole in the substrate extending from the front surface to a predetermined depth;

filing the hole with an electrode material;

forming a wiring layer on the rear surface, the wiring layer comprised of an insulating film containing wires;

reducing a thickness of the substrate until the hole extend to the rear surface;

removing a portion of the gate insulating film; and

forming a charge fixing film across the rear surface with the charge fixing film extending into that portion of the hole where the gate insulating film was removed.

9. The method of claim 8, wherein the substrate is a bulk substrate.

10. The method of claim 8, wherein the substrate is an SOI substrate having a monocrystal silicon layer on a silicon oxide layer on a silicon substrate.

11. The method of claim 10, wherein the hole is formed to a depth such that it extends through the silicon oxide layer and the monocrystal silicon layer.

12. The method of claim 8, wherein the step of reducing of the thickness of the substrate comprises wet etching the substrate a plurality of times.

13. The method of claim 8, further comprising forming at least one insulating film on the charge fixing film after the charge fixing film is formed.

14. The method of claim 8, wherein the charge fixing film comprises two or more kinds of layers stacked together.