Methods of forming printable integrated circuit devices and devices formed thereby

• US 9,040,425 B2
• Filed: 07/17/2014
• Issued: 05/26/2015
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Semprius, Inc.
• Inventors: Bower, Christopher, Menard, Etienne, Meitl, Matthew, Carr, Joseph
• Primary Examiner(s): HENRY, CALEB E
• Application Number:
  US14/334,179
• Publication Number:
  US 20150079783A1
• Time in Patent Office: 313 Days
• Field of Search: 438/700, 438/118, 438/458, 257/E21.214
• US Class Current: 438/700
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate

Abstract

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Claims

1. A method of forming an integrated circuit device, comprising:

forming a sacrificial layer on a handling substrate;

forming a semiconductor active layer on the sacrificial layer;

selectively etching through the semiconductor active layer and the sacrificial layer to define a patterned substrate comprising a first portion of the semiconductor active layer;

forming a multi-layer electrical interconnect network on the patterned substrate;

encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer;

selectively etching through the inorganic capping layer and the first portion of the semiconductor active layer to expose the sacrificial layer; and

selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the inorganic capping layer.

2. The method of claim 1, wherein said encapsulating is preceded by roughening the upper surface of the first portion of the semiconductor active layer.

3. The method of claim 2, wherein said roughening the upper surface of the first portion of the semiconductor active layer comprises exposing the upper surface to a plasma etchant.

4. The method of claim 1, wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate;

and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

5. The method of claim 4, wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.

6. The method of claim 4, wherein the trench is a ring-shaped trench that surrounds the patterned substrate.

7. The method of claim 4, wherein filling the trench with an inorganic anchor comprises depositing a semiconductor layer into the trench and onto the patterned substrate and then planarizing the deposited semiconductor layer to define a semiconductor anchor.

8. The method of claim 4, wherein the multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers;

and wherein said encapsulating is preceded by a step of selectively etching through the plurality of interlayer dielectric layers to expose the inorganic anchor.

9. The method of claim 8, wherein said encapsulating comprises depositing the inorganic capping layer onto the exposed inorganic anchor.

10. The method of claim 8, wherein the inorganic capping layer comprises amorphous silicon and the inorganic anchor comprises polysilicon.

11. The method of claim 3, wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate;

and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

12. The method of claim 11, wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.

13. The method of claim 11, wherein the trench is a rectangular ring-shaped trench that surrounds the patterned substrate.

14. The method of claim 11, wherein filling the trench with an inorganic anchor comprises depositing a polysilicon layer into the trench and onto the patterned substrate and then removing excess portions of the deposited polysilicon layer using a planarization technique to define a semiconductor anchor.

15. The method of claim 11, wherein the multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers;

and wherein said encapsulating is preceded by a step of selectively etching through the plurality of interlayer dielectric layers to expose the inorganic anchor.

16. The method of claim 15, wherein said encapsulating comprises depositing an amorphous silicon capping layer onto the exposed inorganic anchor.

17. The method of claim 1, wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate;

and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

18. The method of claim 17, wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.