Semiconductor device and manufacturing method thereof

• US 9,040,989 B2
• Filed: 09/09/2013
• Issued: 05/26/2015
• Est. Priority Date: 12/08/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/021,406
• Publication Number:
  US 20140008648A1
• Time in Patent Office: 624 Days
• Field of Search: 257/57, 257/59, 257/E21.41, 257/E29.296, 257/E29.003
• US Class Current: 257/57
• CPC Class Codes: H01L 21/3003 Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.

Claims

1. A semiconductor device comprising:

a first gate electrode;

an oxide semiconductor layer over the first gate electrode, the oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction, wherein an angle between the direction and a surface of the oxide semiconductor layer is within a range of 80°

to 100°

;

a second gate electrode over the oxide semiconductor layer;

a nitride insulating layer containing hydrogen over the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is in a non-single-crystal state.

3. The semiconductor device according to claim 1, wherein the second gate electrode is positioned under the nitride insulating layer.

4. The semiconductor device according to claim 1, wherein off-state current density of a transistor comprising the oxide semiconductor layer is 100 aA/μ

m or less.

5. The semiconductor device according to claim 1, wherein off-state resistivity of a transistor comprising the oxide semiconductor layer is greater than or equal to 1×

10⁹ Ω

·

m.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises In—

Ga—

Zn—

O based oxide.

7. A semiconductor device comprising:

a first gate electrode;

an oxide semiconductor layer over the first gate electrode, the oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction, wherein an angle between the direction and a surface of the oxide semiconductor layer is within a range of 80°

to 100°

;

an oxide insulating layer over the oxide semiconductor layer;

a second gate electrode over the oxide semiconductor layer;

a nitride insulating layer containing hydrogen over the oxide insulating layer.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor layer is in a non-single-crystal state.

9. The semiconductor device according to claim 7, wherein the second gate electrode is positioned between the oxide insulating layer and the nitride insulating layer.

10. The semiconductor device according to claim 7, wherein off-state current density of a transistor comprising the oxide semiconductor layer is 100 aA/μ

m or less.

11. The semiconductor device according to claim 7, wherein off-state resistivity of a transistor comprising the oxide semiconductor layer is greater than or equal to 1×

10⁹ Ω

·

m.

12. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises In—

Ga—

Zn—

O based oxide.

13. A semiconductor device comprising:

a first conductive layer;

an oxide semiconductor layer over the first conductive layer, the oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction, wherein an angle between the direction and a surface of the oxide semiconductor layer is within a range of 80°

to 100°

;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer;

a second conductive layer over the oxide semiconductor layer;

a nitride insulating layer containing hydrogen over the oxide semiconductor layer.

14. The semiconductor device according to claim 13, wherein each of the first conductive layer and the second conductive layer is a gate electrode.

15. The semiconductor device according to claim 13, further comprising an oxide insulating layer between the oxide semiconductor layer and the nitride insulating layer.

16. The semiconductor device according to claim 13, wherein the oxide semiconductor layer is in a non-single-crystal state.

17. The semiconductor device according to claim 13, wherein the second conductive layer is positioned under the nitride insulating layer.

18. The semiconductor device according to claim 13, wherein off-state current density of a transistor comprising the oxide semiconductor layer is 100 aA/μ

m or less.

19. The semiconductor device according to claim 13, wherein off-state resistivity of a transistor comprising the oxide semiconductor layer is greater than or equal to 1×

10⁹ Ω

·

m.

20. The semiconductor device according to claim 13, wherein the oxide semiconductor layer comprises In—

Ga—

Zn—

O based oxide.

21. A semiconductor device comprising:

a first conductive layer;

an oxide semiconductor layer over the first conductive layer, the oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer;

a second conductive layer over the oxide semiconductor layer;

a nitride insulating layer containing hydrogen over the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises an oxide comprising indium.

22. The semiconductor device according to claim 21, wherein each of the first conductive layer and the second conductive layer is a gate electrode.

23. The semiconductor device according to claim 21, further comprising an oxide insulating layer between the oxide semiconductor layer and the nitride insulating layer.

24. The semiconductor device according to claim 21, wherein the oxide semiconductor layer is in a non-single-crystal state.

25. The semiconductor device according to claim 21, wherein the second conductive layer is positioned under the nitride insulating layer.

26. The semiconductor device according to claim 21, wherein off-state current density of a transistor comprising the oxide semiconductor layer is 100 aA/μ

m or less.

27. The semiconductor device according to claim 21, wherein off-state resistivity of a transistor comprising the oxide semiconductor layer is greater than or equal to 1×

10⁹ Ω

·

m.

28. The semiconductor device according to claim 21, wherein the oxide semiconductor layer comprises In—

Ga—

Zn—

O based oxide.