Semiconductor device

• US 9,041,007 B2
• Filed: 11/18/2011
• Issued: 05/26/2015
• Est. Priority Date: 11/25/2010
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Suekawa, Eisuke, Oritsuki, Yasunori, Tarui, Yoichiro
• Primary Examiner(s): Tran, Tan N
• Assistant Examiner(s): Wilson, Scott R
• Application Number:
  US13/299,882
• Publication Number:
  US 20120132912A1
• Time in Patent Office: 1,285 Days
• Field of Search: None
• US Class Current: 257/77
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n⁺-source region formed in an upper portion of an n⁻-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Claims

1. A semiconductor device, comprising:

a main transistor cell with a gate insulating film formed on a silicon carbide semiconductor layer, a gate electrode formed on said gate insulating film, and a source region that is an impurity region formed in an upper portion of said semiconductor layer;

an interlayer insulating film in direct contact with said gate electrode;

a source electrode connected to said source region while extending over said interlayer insulating film;

a gate pad connected to said gate electrode; and

a barrier metal layer interposed between said source electrode and said interlayer insulating film, and between said gate pad and said gate electrode, said barrier metal layer formed both over said source region and under said gate pad, said barrier metal layer contacting a horizontal surface of said interlayer insulating film.

2. The semiconductor device according to claim 1, further comprising a current sensing cell, the current sensing cell having a gate electrode shared with said main transistor cell, the current sensing cell having a source electrode including aluminum that is different from that of said main transistor cell,

wherein said barrier metal layer is also interposed between said source electrode of said current sensing cell and said interlayer insulating film.

3. The semiconductor device according to claim 1, wherein said barrier metal layer is a TiN layer having a thickness of 90nm or more.

4. The semiconductor device according to claim 1, further comprising a compound layer of said semiconductor layer and metal, the compound layer being formed at part of said source region in contact with said source electrode.

5. The semiconductor device according to claim 1, wherein:

a thickness of the barrier metal layer is greater than or equal to 90nm.

6. The semiconductor device according to claim 1, wherein:

the source electrode includes aluminum;

the gate pad includes aluminum; and

the barrier metal layer prevents diffusion of aluminum.

7. The semiconductor device according to claim 1, wherein:

said barrier metal layer extends continuously from the top portion of said interlayer insulating film to the side portion of said interlayer insulating film.

8. The semiconductor device according to claim 1, wherein:

said barrier metal layer has been patterned together with said source electrode and said gate pad.

9. The semiconductor device according to claim 1, further comprising:

a silicide layer in ohmic contact with said source region, said silicide layer disposed between said source region and said source electrode.

10. The semiconductor device according to claim 9, wherein:

said barrier metal layer is disposed between said silicide layer and said source electrode.